Push/pop and other calling convention lowering conditionalized

A number of calling convention related changes were made unconditionally.
This makes these conditionalized, although there are still some small
differences I would like to address separately in the logs for struct_byval.ll

BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711

Review URL: https://codereview.chromium.org/11416053

2 files changed, 31 insertions, 23 deletions

diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp
index c8ddbcfaec..f9ab225fe5 100644
--- a/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/lib/Target/ARM/ARMFrameLowering.cpp
@@ -159,9 +159,10 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
   // @LOCALMOD-START
   MachineModuleInfo &MMI = MF.getMMI();
   // This condition was gleaned from x86 / PowerPC / XCore
-  bool needsFrameMoves = MMI.hasDebugInfo() ||
-                         !MF.getFunction()->doesNotThrow() ||
-                         MF.getFunction()->needsUnwindTableEntry();
+  bool needsFrameMoves = STI.isTargetNaCl() &&
+                         (MMI.hasDebugInfo() ||
+                          !MF.getFunction()->doesNotThrow() ||
+                          MF.getFunction()->needsUnwindTableEntry());
   // @LOCALMOD-END
   
   // All calls are tail calls in GHC calling conv, and functions have no
@@ -752,7 +753,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
         continue;
 
       if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps() &&
-          false /* @LOCALMOD */) {
+          !STI.isTargetNaCl() /* @LOCALMOD */) {
         Reg = ARM::PC;
         LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
         // Fold the return instruction into the LDM.
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 0893826427..752a492c61 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -682,17 +682,22 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
     // Non-Darwin platforms may return values in these registers via the
     // personality function.
     setOperationAction(ISD::EHSELECTION,      MVT::i32,   Expand);
-    // @LOCALMOD-START
     setOperationAction(ISD::EXCEPTIONADDR,    MVT::i32,   Expand);
-    // we use the first caller saved regs here
-    // c.f.: llvm-gcc/llvm-gcc-4.2/gcc/unwind-dw2.c::uw_install_context
-    // NOTE: these are related to the _Unwind_PNaClSetResult{0,1} functions
-    setExceptionPointerRegister(ARM::R4);
-    setExceptionSelectorRegister(ARM::R5);
-
-    setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
+    // @LOCALMOD-START
+    if (Subtarget->isTargetNaCl()) {
+      // we use the first caller saved regs here
+      // c.f.: llvm-gcc/llvm-gcc-4.2/gcc/unwind-dw2.c::uw_install_context
+      // NOTE: these are related to the _Unwind_PNaClSetResult{0,1} functions
+      setExceptionPointerRegister(ARM::R4);
+      setExceptionSelectorRegister(ARM::R5);
+  
+      setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
 
-    setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
+      setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
+    } else {
+      setExceptionPointerRegister(ARM::R0);
+      setExceptionSelectorRegister(ARM::R1);
+    }
     // @LOCALMOD-END
   }
 
@@ -1712,15 +1717,17 @@ ARMTargetLowering::HandleByVal(
   // a byval param that forced this, so that we know not to use the
   // handle var-args reg-save area.
   // PR11018.
-  if ((!State->isFirstByValRegValid()) &&
-      (ARM::R0 <= reg) && (reg <= ARM::R3)) {
-    State->setHasByValInRegPosition();
+  if (Subtarget->isTargetNaCl()) {
+    if ((!State->isFirstByValRegValid()) &&
+        (ARM::R0 <= reg) && (reg <= ARM::R3)) {
+      State->setHasByValInRegPosition();
+    }
+    // Confiscate any remaining parameter registers to preclude their
+    // assignment to subsequent parameters.
+    while (State->AllocateReg(GPRArgRegs, 4))
+      ;
+    return;
   }
-  // Confiscate any remaining parameter registers to preclude their
-  // assignment to subsequent parameters.
-  while (State->AllocateReg(GPRArgRegs, 4))
-    ;
-  return;
   // @LOCALMOD-END
 
   if ((!State->isFirstByValRegValid()) &&
@@ -2753,7 +2760,7 @@ ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
   if (CCInfo.isFirstByValRegValid())
     NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
     // @LOCALMOD-BEGIN
-  else if (CCInfo.hasByValInRegPosition())
+  else if (Subtarget->isTargetNaCl() && CCInfo.hasByValInRegPosition())
     NumGPRs = 0;
     // @LOCALMOD-END
   else {
@@ -2790,7 +2797,7 @@ ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
   if (CCInfo.isFirstByValRegValid())
     firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
   // @LOCALMOD-BEGIN
-  else if (CCInfo.hasByValInRegPosition())
+  else if (Subtarget->isTargetNaCl() && CCInfo.hasByValInRegPosition())
     firstRegToSaveIndex = 4; // Nothing to save.
   // @LOCALMOD-END
   else {