diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-22 17:56:58 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-22 17:56:58 +0000 |
| commit | b113ec55e897c85fda606409c1eedec4f89ec53f (patch) | |
| tree | 90208d469d2de79dbdb8baac226d270e21ee45dd | |
| parent | 011af5ca801cb95117a9abe2b217f78e2a7c8899 (diff) | |
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb1.txt | 30 |
2 files changed, 31 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index a57102c6e1..ebcb798969 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2322,7 +2322,7 @@ static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateImm(Val << 2)); + Inst.addOperand(MCOperand::CreateImm(Val)); return Success; } diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index 24917735b8..5b02a58f0c 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -101,3 +101,33 @@ 0x6c 0x40 +#------------------------------------------------------------------------------ +# LDM +#------------------------------------------------------------------------------ +# CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} +# CHECK: ldm r2!, {r1, r3, r4, r5, r7} +# CHECK: ldm r1, {r1} + +0xff 0xcb +0xba 0xca +0x02 0xc9 + + +#------------------------------------------------------------------------------ +# LDR (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldr r1, [r5] +# CHECK: ldr r2, [r6, #32] +# CHECK: ldr r3, [r7, #124] +# CHECK: ldr r1, [sp] +# CHECK: ldr r2, [sp, #24] +# CHECK: ldr r3, [sp, #1020] + + +0x29 0x68 +0x32 0x6a +0xfb 0x6f +0x00 0x99 +0x06 0x9a +0xff 0x9b + |