Add tests for auto-updating version of vld[1-4]

4 files changed, 91 insertions, 2 deletions

diff --git a/test/NaCl/ARM/neon-vld1-sandboxing.ll b/test/NaCl/ARM/neon-vld1-sandboxing.ll
index 52395a559f..bf3dc253a6 100644
--- a/test/NaCl/ARM/neon-vld1-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld1-sandboxing.ll
@@ -79,6 +79,16 @@ declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly
 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
 
+define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
+  %A = load i8** %ptr
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
+; CHECK:         bic r1, r1, #3221225472
+; CHECK-NEXT:    vld1.8 {{{d[0-9]+}}, {{d[0-9]+}}}, [r1, :64]!
+  %tmp2 = getelementptr i8* %A, i32 16
+  store i8* %tmp2, i8** %ptr
+  ret <16 x i8> %tmp1
+}
+
 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
   %A = load i16** %ptr
   %tmp0 = bitcast i16* %A to i8*
@@ -90,3 +100,14 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
   ret <4 x i16> %tmp1
 }
 
+define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
+  %A = load i32** %ptr
+  %tmp0 = bitcast i32* %A to i8*
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
+; CHECK:         bic r2, r2, #3221225472
+; CHECK-NEXT:    vld1.32 {{{d[0-9]+}}}, [r2], r1
+  %tmp2 = getelementptr i32* %A, i32 %inc
+  store i32* %tmp2, i32** %ptr
+  ret <2 x i32> %tmp1
+}
+
diff --git a/test/NaCl/ARM/neon-vld2-sandboxing.ll b/test/NaCl/ARM/neon-vld2-sandboxing.ll
index ffec745e5f..b67a9bf4d1 100644
--- a/test/NaCl/ARM/neon-vld2-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld2-sandboxing.ll
@@ -87,7 +87,6 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind {
   ret <4 x i32> %tmp4
 }
 
-;Check for a post-increment updating load with register increment.
 define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
   %A = load i8** %ptr
   %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
@@ -100,3 +99,18 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
   store i8* %tmp5, i8** %ptr
   ret <16 x i8> %tmp4
 }
+
+define <2 x float> @vld2f_update(float** %ptr) nounwind {
+  %A = load float** %ptr
+  %tmp0 = bitcast float* %A to i8*
+  %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
+; CHECK: bic       r1, r1, #3221225472
+; CHECK: vld2.32   {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
+  %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+  %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+  %tmp4 = fadd <2 x float> %tmp2, %tmp3
+  %tmp5 = getelementptr float* %A, i32 4
+  store float* %tmp5, float** %ptr
+  ret <2 x float> %tmp4
+}
+
diff --git a/test/NaCl/ARM/neon-vld3-sandboxing.ll b/test/NaCl/ARM/neon-vld3-sandboxing.ll
index 49e38b9c77..749a913fd4 100644
--- a/test/NaCl/ARM/neon-vld3-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld3-sandboxing.ll
@@ -66,7 +66,6 @@ define <1 x i64> @vld3i64(i64* %A) nounwind {
   ret <1 x i64> %tmp4
 }
 
-
 define <16 x i8> @vld3Qi8(i8* %A) nounwind {
   %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
   %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
@@ -77,3 +76,31 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind {
   ret <16 x i8> %tmp4
 }
 
+define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
+  %A = load i16** %ptr
+  %tmp0 = bitcast i16* %A to i8*
+  %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
+; CHECK:         bic r2, r2, #3221225472
+; CHECK-NEXT:    vld3.16  {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r2], r1
+  %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
+  %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
+  %tmp4 = add <4 x i16> %tmp2, %tmp3
+  %tmp5 = getelementptr i16* %A, i32 %inc
+  store i16* %tmp5, i16** %ptr
+  ret <4 x i16> %tmp4
+}
+
+define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
+  %A = load i32** %ptr
+  %tmp0 = bitcast i32* %A to i8*
+  %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1)
+; CHECK:         bic r1, r1, #3221225472
+; CHECK-NEXT:    vld3.32  {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r1]!
+  %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
+  %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
+  %tmp4 = add <4 x i32> %tmp2, %tmp3
+  %tmp5 = getelementptr i32* %A, i32 12
+  store i32* %tmp5, i32** %ptr
+  ret <4 x i32> %tmp4
+}
+
diff --git a/test/NaCl/ARM/neon-vld4-sandboxing.ll b/test/NaCl/ARM/neon-vld4-sandboxing.ll
index 14d903c09e..c23a0a6dbf 100644
--- a/test/NaCl/ARM/neon-vld4-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld4-sandboxing.ll
@@ -78,3 +78,30 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind {
   ret <16 x i8> %tmp4
 }
 
+define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
+	%A = load i8** %ptr
+	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
+; CHECK:         bic r2, r2, #3221225472
+; CHECK-NEXT:    vld4.8 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r2, :128], r1
+	%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
+	%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
+	%tmp4 = add <8 x i8> %tmp2, %tmp3
+	%tmp5 = getelementptr i8* %A, i32 %inc
+	store i8* %tmp5, i8** %ptr
+	ret <8 x i8> %tmp4
+}
+
+define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
+	%A = load i16** %ptr
+	%tmp0 = bitcast i16* %A to i8*
+	%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
+; CHECK:         bic r1, r1, #3221225472
+; CHECK-NEXT:    vld4.16 {{{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}}, [r1, :64]!
+	%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
+	%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
+	%tmp4 = add <8 x i16> %tmp2, %tmp3
+	%tmp5 = getelementptr i16* %A, i32 32
+	store i16* %tmp5, i16** %ptr
+	ret <8 x i16> %tmp4
+}
+