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authorDerek Schuff <dschuff@chromium.org>2012-09-19 16:10:54 -0700
committerDerek Schuff <dschuff@chromium.org>2012-09-19 16:10:54 -0700
commit0e15ffd8cb1ec642eddb96380660914ff2b007e1 (patch)
treebc5ccf8c89bfe799bb276625e8e0bd6d84e3a75c
parent5e79ec1d7ada2e14283e2b69b6f4375eb4dd1890 (diff)
parent020aba0c3b6092e353e133446cb6453f95f0d61b (diff)
Merge commit '020aba0c3b6092e353e133446cb6453f95f0d61b'
-rw-r--r--CREDITS.TXT14
-rw-r--r--cmake/platforms/Android.cmake21
-rw-r--r--include/llvm/ADT/FoldingSet.h9
-rw-r--r--include/llvm/CodeGen/MachineScheduler.h218
-rw-r--r--include/llvm/InitializePasses.h1
-rw-r--r--include/llvm/LinkAllPasses.h1
-rw-r--r--include/llvm/MC/MCAsmInfo.h20
-rw-r--r--include/llvm/MC/MCRegisterInfo.h7
-rw-r--r--include/llvm/Object/ELF.h47
-rw-r--r--include/llvm/TableGen/Record.h2
-rw-r--r--include/llvm/Target/TargetRegisterInfo.h34
-rw-r--r--include/llvm/Transforms/IPO.h5
-rw-r--r--include/llvm/Transforms/Utils/BypassSlowDivision.h10
-rw-r--r--include/llvm/Transforms/Utils/SimplifyIndVar.h2
-rw-r--r--lib/CodeGen/AsmPrinter/AsmPrinter.cpp93
-rw-r--r--lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp33
-rw-r--r--lib/CodeGen/AsmPrinter/DIE.cpp3
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp2
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfCompileUnit.h4
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfDebug.cpp7
-rw-r--r--lib/CodeGen/AsmPrinter/DwarfDebug.h3
-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp4
-rw-r--r--lib/CodeGen/LiveVariables.cpp34
-rw-r--r--lib/CodeGen/MachineScheduler.cpp356
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp57
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp52
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp40
-rw-r--r--lib/CodeGen/StackColoring.cpp99
-rw-r--r--lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp3
-rw-r--r--lib/MC/MCAsmInfo.cpp2
-rw-r--r--lib/MC/MCAsmInfoCOFF.cpp4
-rw-r--r--lib/MC/MCAsmInfoDarwin.cpp1
-rw-r--r--lib/MC/MCAsmStreamer.cpp16
-rw-r--r--lib/MC/MCMachOStreamer.cpp13
-rw-r--r--lib/MC/MCParser/AsmParser.cpp13
-rw-r--r--lib/MC/MCParser/ELFAsmParser.cpp2
-rw-r--r--lib/MC/MCRegisterInfo.cpp3
-rw-r--r--lib/Support/FoldingSet.cpp18
-rw-r--r--lib/Support/Memory.cpp4
-rw-r--r--lib/Support/Unix/Memory.inc8
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp10
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp10
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp1
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp2
-rw-r--r--lib/Target/Hexagon/HexagonMachineScheduler.cpp464
-rw-r--r--lib/Target/Hexagon/HexagonMachineScheduler.h324
-rw-r--r--lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp2
-rw-r--r--lib/Target/Mips/AsmParser/MipsAsmParser.cpp3
-rw-r--r--lib/Target/Mips/MipsAsmPrinter.cpp2
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp1
-rw-r--r--lib/Target/TargetRegisterInfo.cpp6
-rw-r--r--lib/Target/X86/AsmParser/X86AsmParser.cpp5
-rw-r--r--lib/Target/X86/Disassembler/X86Disassembler.h2
-rw-r--r--lib/Target/X86/Disassembler/X86DisassemblerDecoder.h2
-rw-r--r--lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp6
-rw-r--r--lib/Target/X86/InstPrinter/X86ATTInstPrinter.h2
-rw-r--r--lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp6
-rw-r--r--lib/Target/X86/InstPrinter/X86IntelInstPrinter.h2
-rw-r--r--lib/Target/X86/X86AsmPrinter.cpp14
-rw-r--r--lib/Target/X86/X86AsmPrinter.h4
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp248
-rw-r--r--lib/Target/X86/X86ISelLowering.h25
-rw-r--r--lib/Target/X86/X86InstrFragmentsSIMD.td4
-rw-r--r--lib/Target/X86/X86InstrInfo.td4
-rw-r--r--lib/Target/X86/X86InstrSSE.td70
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp2
-rw-r--r--lib/Transforms/Scalar/DeadStoreElimination.cpp10
-rw-r--r--lib/Transforms/Scalar/GVN.cpp8
-rw-r--r--lib/Transforms/Utils/BypassSlowDivision.cpp10
-rw-r--r--lib/Transforms/Utils/CMakeLists.txt1
-rw-r--r--lib/Transforms/Utils/MetaRenamer.cpp132
-rw-r--r--lib/Transforms/Utils/SimplifyCFG.cpp160
-rw-r--r--lib/Transforms/Utils/Utils.cpp1
-rw-r--r--lib/VMCore/Core.cpp6
-rw-r--r--test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll31
-rw-r--r--test/CodeGen/ARM/crash-shufflevector.ll10
-rw-r--r--test/CodeGen/ARM/sub-cmp-peephole.ll21
-rw-r--r--test/CodeGen/X86/StackColoring-dbg.ll30
-rw-r--r--test/CodeGen/X86/StackColoring.ll90
-rw-r--r--test/CodeGen/X86/avx-basic.ll4
-rw-r--r--test/CodeGen/X86/avx2-shuffle.ll25
-rw-r--r--test/CodeGen/X86/bool-simplify.ll18
-rw-r--r--test/CodeGen/X86/ms-inline-asm.ll14
-rw-r--r--test/CodeGen/X86/vec_fabs.ll38
-rw-r--r--test/CodeGen/X86/vec_floor.ll38
-rw-r--r--test/CodeGen/X86/vec_fpext.ll32
-rw-r--r--test/DebugInfo/X86/pr13303.ll28
-rw-r--r--test/MC/AsmParser/directive_lcomm.s11
-rw-r--r--test/MC/AsmParser/labels.s2
-rw-r--r--test/MC/COFF/comm.ll13
-rw-r--r--test/MC/ELF/lcomm.s21
-rw-r--r--test/MC/Mips/mips-relocations.s41
-rw-r--r--test/MC/X86/intel-syntax-2.s6
-rw-r--r--test/Transforms/MetaRenamer/lit.local.cfg1
-rw-r--r--test/Transforms/MetaRenamer/metarenamer.ll96
-rw-r--r--test/Transforms/SimplifyCFG/preserve-branchweights-partial.ll37
-rw-r--r--test/Transforms/SimplifyCFG/preserve-branchweights-switch-create.ll92
-rw-r--r--utils/FileCheck/FileCheck.cpp6
-rw-r--r--utils/TableGen/CodeGenRegisters.cpp58
-rw-r--r--utils/TableGen/CodeGenRegisters.h10
-rw-r--r--utils/TableGen/DFAPacketizerEmitter.cpp168
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp24
-rw-r--r--utils/TableGen/X86DisassemblerTables.cpp4
-rw-r--r--utils/lit/lit/Util.py2
-rw-r--r--utils/unittest/googletest/gtest-port.cc4
105 files changed, 2248 insertions, 1541 deletions
diff --git a/CREDITS.TXT b/CREDITS.TXT
index f090ad734c..b5aa2580e1 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -5,8 +5,8 @@ done!
The list is sorted by surname and formatted to allow easy grepping and
beautification by scripts. The fields are: name (N), email (E), web-address
-(W), PGP key ID and fingerprint (P), description (D), and snail-mail address
-(S).
+(W), PGP key ID and fingerprint (P), description (D), snail-mail address
+(S), and (I) IRC handle.
N: Vikram Adve
@@ -328,10 +328,6 @@ D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
-N: Sandeep Patel
-E: deeppatel1987@gmail.com
-D: ARM calling conventions rewrite, hard float support
-
N: Wesley Peck
E: peckw@wesleypeck.com
W: http://wesleypeck.com/
@@ -354,6 +350,11 @@ N: Xerxes Ranby
E: xerxes@zafena.se
D: Cmake dependency chain and various bug fixes
+N: Alex Rosenberg
+E: alexr@leftfield.org
+I: arosenberg
+D: ARM calling conventions rewrite, hard float support
+
N: Chad Rosier
E: mcrosier@apple.com
D: ARM fast-isel improvements
@@ -369,6 +370,7 @@ D: MSIL backend
N: Duncan Sands
E: baldrick@free.fr
+I: baldrick
D: Ada support in llvm-gcc
D: Dragonegg plugin
D: Exception handling improvements
diff --git a/cmake/platforms/Android.cmake b/cmake/platforms/Android.cmake
new file mode 100644
index 0000000000..72849b16c7
--- /dev/null
+++ b/cmake/platforms/Android.cmake
@@ -0,0 +1,21 @@
+# Toolchain config for Android NDK.
+# This is expected to be used with a standalone Android toolchain (see
+# docs/STANDALONE-TOOLCHAIN.html in the NDK on how to get one).
+#
+# Usage:
+# mkdir build; cd build
+# cmake ..; make
+# mkdir android; cd android
+# cmake -DLLVM_ANDROID_TOOLCHAIN_DIR=/path/to/android/ndk \
+# -DCMAKE_TOOLCHAIN_FILE=../../cmake/platforms/Android.cmake ../..
+# make <target>
+
+SET(CMAKE_SYSTEM_NAME Linux)
+SET(CMAKE_C_COMPILER ${CMAKE_BINARY_DIR}/../bin/clang)
+SET(CMAKE_CXX_COMPILER ${CMAKE_BINARY_DIR}/../bin/clang++)
+SET(ANDROID "1" CACHE STRING "ANDROID" FORCE)
+
+SET(ANDROID_COMMON_FLAGS "-target arm-linux-androideabi --sysroot=${LLVM_ANDROID_TOOLCHAIN_DIR}/sysroot -B${LLVM_ANDROID_TOOLCHAIN_DIR} -mllvm -arm-enable-ehabi")
+SET(CMAKE_C_FLAGS "${ANDROID_COMMON_FLAGS}" CACHE STRING "toolchain_cflags" FORCE)
+SET(CMAKE_CXX_FLAGS "${ANDROID_COMMON_FLAGS}" CACHE STRING "toolchain_cxxflags" FORCE)
+SET(CMAKE_LINK_FLAGS "${ANDROID_COMMON_FLAGS}" CACHE STRING "toolchain_linkflags" FORCE)
diff --git a/include/llvm/ADT/FoldingSet.h b/include/llvm/ADT/FoldingSet.h
index ba415ac2d6..375d84abeb 100644
--- a/include/llvm/ADT/FoldingSet.h
+++ b/include/llvm/ADT/FoldingSet.h
@@ -278,6 +278,10 @@ public:
bool operator==(FoldingSetNodeIDRef) const;
+ /// Used to compare the "ordering" of two nodes as defined by the
+ /// profiled bits and their ordering defined by memcmp().
+ bool operator<(FoldingSetNodeIDRef) const;
+
const unsigned *getData() const { return Data; }
size_t getSize() const { return Size; }
};
@@ -327,6 +331,11 @@ public:
bool operator==(const FoldingSetNodeID &RHS) const;
bool operator==(const FoldingSetNodeIDRef RHS) const;
+ /// Used to compare the "ordering" of two nodes as defined by the
+ /// profiled bits and their ordering defined by memcmp().
+ bool operator<(const FoldingSetNodeID &RHS) const;
+ bool operator<(const FoldingSetNodeIDRef RHS) const;
+
/// Intern - Copy this node's data to a memory region allocated from the
/// given allocator and return a FoldingSetNodeIDRef describing the
/// interned data.
diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h
index 8da2045ad0..f87c2a5c40 100644
--- a/include/llvm/CodeGen/MachineScheduler.h
+++ b/include/llvm/CodeGen/MachineScheduler.h
@@ -28,9 +28,16 @@
#define MACHINESCHEDULER_H
#include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/MC/MCInstrItineraries.h"
namespace llvm {
+extern cl::opt<bool> ForceTopDown;
+extern cl::opt<bool> ForceBottomUp;
+
class AliasAnalysis;
class LiveIntervals;
class MachineDominatorTree;
@@ -93,6 +100,217 @@ public:
}
};
+class ScheduleDAGMI;
+
+/// MachineSchedStrategy - Interface to the scheduling algorithm used by
+/// ScheduleDAGMI.
+class MachineSchedStrategy {
+public:
+ virtual ~MachineSchedStrategy() {}
+
+ /// Initialize the strategy after building the DAG for a new region.
+ virtual void initialize(ScheduleDAGMI *DAG) = 0;
+
+ /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
+ /// schedule the node at the top of the unscheduled region. Otherwise it will
+ /// be scheduled at the bottom.
+ virtual SUnit *pickNode(bool &IsTopNode) = 0;
+
+ /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
+ /// instruction and updated scheduled/remaining flags in the DAG nodes.
+ virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
+
+ /// When all predecessor dependencies have been resolved, free this node for
+ /// top-down scheduling.
+ virtual void releaseTopNode(SUnit *SU) = 0;
+ /// When all successor dependencies have been resolved, free this node for
+ /// bottom-up scheduling.
+ virtual void releaseBottomNode(SUnit *SU) = 0;
+};
+
+/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
+/// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
+/// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
+///
+/// This is a convenience class that may be used by implementations of
+/// MachineSchedStrategy.
+class ReadyQueue {
+ unsigned ID;
+ std::string Name;
+ std::vector<SUnit*> Queue;
+
+public:
+ ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
+
+ unsigned getID() const { return ID; }
+
+ StringRef getName() const { return Name; }
+
+ // SU is in this queue if it's NodeQueueID is a superset of this ID.
+ bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
+
+ bool empty() const { return Queue.empty(); }
+
+ unsigned size() const { return Queue.size(); }
+
+ typedef std::vector<SUnit*>::iterator iterator;
+
+ iterator begin() { return Queue.begin(); }
+
+ iterator end() { return Queue.end(); }
+
+ iterator find(SUnit *SU) {
+ return std::find(Queue.begin(), Queue.end(), SU);
+ }
+
+ void push(SUnit *SU) {
+ Queue.push_back(SU);
+ SU->NodeQueueId |= ID;
+ }
+
+ void remove(iterator I) {
+ (*I)->NodeQueueId &= ~ID;
+ *I = Queue.back();