diff options
| author | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 05:47:56 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 05:47:56 +0000 |
| commit | ca7943226e1d58f4f3ae936f93aa03c2a72289ae (patch) | |
| tree | b0e6a2e02cf7743b889fa4f79a36ff4bf15143dd | |
| parent | cc0a0299d96676e0a51e9b8f5bf617d8025f09a7 (diff) | |
Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80338 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index b0108f2306..bc485daf6e 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1058,12 +1058,11 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, return; const TargetInstrDesc &Desc = MI.getDesc(); - unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); // If we get here, the immediate doesn't fit into the instruction. We folded // as much as possible above, handle the rest, providing a register that is // SP+LargeImm. - assert((Offset || AddrMode == ARMII::AddrMode4) && + assert((Offset || (Desc.TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && "This code isn't needed if offset already handled!"); // Insert a set of r12 with the full address: r12 = sp + offset |