diff options
| author | JF Bastien <jfb@chromium.org> | 2013-07-10 16:11:27 -0700 |
|---|---|---|
| committer | JF Bastien <jfb@chromium.org> | 2013-07-10 16:11:27 -0700 |
| commit | eff7428a4cd1ffcbf4800bd0c502262da361c872 (patch) | |
| tree | 78de6e3c4f7676b2717ed00cfb33f1cb6e7cbf18 | |
| parent | a7324c581f3f66acfbf98e18dee3d919d85af16d (diff) | |
Fix ARM LDMIA MI.
The instruction that was generated for paired register stack slot load was wrong. This was fixed by Tim Northover in LLVM 3.3 commit 179977, but his patch does much more and doesn't apply as-is to our tree. I'll therefore punt applying the full patch to when we rebase to 3.3.
I encountered the issue while working on atomics (64-bit atomics require paired registers on ARM), and saw the 3.3 fix when I tried upstreaming my fix.
BUG= non
TEST= ./pnacl/test.sh test-arm
R=eliben@chromium.org
Review URL: https://codereview.chromium.org/18699004
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 184e7191e5..5639f01490 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -978,7 +978,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA : ARM::LDMIA; MachineInstrBuilder MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(LdmOpc)) - .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); +// @LOCALMOD-START Fixed in LLVM 3.3 by 179977. This will merge conflict. + .addFrameIndex(FI).addMemOperand(MMO)); +// @LOCALMOD-END MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); if (TargetRegisterInfo::isPhysicalRegister(DestReg)) |