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| author | Craig Topper <craig.topper@gmail.com> | 2012-05-01 05:41:41 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-05-01 05:41:41 +0000 |
| commit | e106d2e2ac0ccd822b78e258a79a9814ed0fa009 (patch) | |
| tree | d9382385e8ee6622c6e5f779b3d73f3b723a0a46 | |
| parent | c49c6e154a6d4374f8df039122dddc1b09bddb38 (diff) | |
Make XOP imply AVX as its needed to legalize the registers types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 14b6b24698..40c96676b1 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -96,7 +96,8 @@ def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", "Enable four-operand fused multiple-add", [FeatureAVX]>; def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", - "Enable XOP instructions">; + "Enable XOP instructions", + [FeatureAVX]>; def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", "HasVectorUAMem", "true", "Allow unaligned memory operands on vector/SIMD instructions">; |