diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-05-18 21:45:49 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-05-18 21:45:49 +0000 |
| commit | dc124a234a02ea6fc1061a51ade1bb7b817ddb61 (patch) | |
| tree | f14d00c3c86fc878f8bd1dcd3456bf61449620db | |
| parent | ffd4364bb0cd7215412cbdfabe1bd7372e475c13 (diff) | |
implement movri
add a stub LowerFORMAL_ARGUMENTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28388 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 9 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
3 files changed, 14 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index ec2b145f9a..57090b98e4 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -81,11 +81,17 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); } +static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { + assert(0 && "Not implemented"); +} + SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); abort(); + case ISD::FORMAL_ARGUMENTS: + return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::RET: return LowerRET(Op, DAG); } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 318c230586..f706927533 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -42,6 +42,8 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; +def BX: InstARM<(ops), "bx", [(retflag)]>; + def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr), "ldr $dst, [$addr]", [(set IntRegs:$dst, (load IntRegs:$addr))]>; @@ -50,5 +52,8 @@ def str : InstARM<(ops IntRegs:$src, IntRegs:$addr), "str $src, [$addr]", [(store IntRegs:$src, IntRegs:$addr)]>; -def mov : InstARM<(ops IntRegs:$dst, IntRegs:$b), - "mov $dst, $b", []>; +def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src), + "mov $dst, $src", []>; + +def movri : InstARM<(ops IntRegs:$dst, i32imm:$src), + "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index e56eef4724..18e273134c 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -49,7 +49,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg); } MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, |