diff options
| author | Andrew Trick <atrick@apple.com> | 2011-01-24 19:08:15 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-01-24 19:08:15 +0000 |
| commit | c48d50f9c036b48826e75df125d80af596980e00 (patch) | |
| tree | c4d6ac53712632037115dd4c639cb8f74252ca45 | |
| parent | bd1801b5553c8be3960255a92738464e0010b6f6 (diff) | |
Temporarily workaround JM/lencod miscompile (SIGSEGV).
rdar://problem/8893967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index ad835806a4..87739c0391 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1645,11 +1645,13 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only // counts data deps. To be more precise, we could maintain a // NumDataSuccsLeft count. + /* FIXME: exposing a downstream bug, JM/lencode miscompile if (PredSU->NumSuccsLeft != PredSU->Succs.size()) { DEBUG(dbgs() << " SU(" << PredSU->NodeNum << ") live across SU(" << SU->NodeNum << ")\n"); continue; } + */ const SDNode *PN = PredSU->getNode(); if (!PN->isMachineOpcode()) { if (PN->getOpcode() == ISD::CopyFromReg) { |