Move VLD cases properly into IsDangerousLoad and update tests that had incorrect -sfi-<xx> flags

BUG=none

Review URL: https://codereview.chromium.org/11759018

10 files changed, 106 insertions, 103 deletions

diff --git a/lib/Target/ARM/ARMNaClRewritePass.cpp b/lib/Target/ARM/ARMNaClRewritePass.cpp
index ccce8879c5..d26a35848d 100644
--- a/lib/Target/ARM/ARMNaClRewritePass.cpp
+++ b/lib/Target/ARM/ARMNaClRewritePass.cpp
@@ -481,100 +481,6 @@ static bool IsDangerousLoad(const MachineInstr &MI, int *AddrIdx) {
   case ARM::LDRD:
     *AddrIdx = 2;
     break;
-  }
-
-  if (MI.getOperand(*AddrIdx).getReg() == ARM::SP) {
-    // The contents of SP do not require masking.
-    return false;
-  }
-
-  return true;
-}
-
-/*
- * Sandboxes a memory reference instruction by inserting an appropriate mask
- * or check operation before it.
- */
-void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator MBBI,
-                                       MachineInstr &MI,
-                                       int AddrIdx,
-                                       bool IsLoad) {
-  unsigned Addr = MI.getOperand(AddrIdx).getReg();
-
-  if (!FlagNaClUseM23ArmAbi && Addr == ARM::R9) {
-    // R9-relative loads are no longer sandboxed.
-    assert(IsLoad && "There should be no r9-relative stores");
-  } else {
-    unsigned Opcode;
-    if (IsLoad && (MI.getOperand(0).getReg() == ARM::SP)) {
-      Opcode = ARM::SFI_GUARD_SP_LOAD;
-    } else {
-      Opcode = ARM::SFI_GUARD_LOADSTORE;
-    }
-    // Use same predicate as current instruction.
-    unsigned PredReg = 0;
-    ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
-    // Use the older BIC sandbox, which is universal, but incurs a stall.
-    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode))
-      .addReg(Addr, RegState::Define)  // Address definition (as dst).
-      .addReg(Addr, RegState::Kill)    // Address read (as src).
-      .addImm((int64_t) Pred)          // predicate condition
-      .addReg(PredReg);                // predicate source register (CPSR)
-
-    /*
-     * This pseudo-instruction is intended to generate something resembling the
-     * following, but with alignment enforced.
-     * TODO(cbiffle): move alignment into this function, use the code below.
-     *
-     *  // bic<cc> Addr, Addr, #0xC0000000
-     *  BuildMI(MBB, MBBI, MI.getDebugLoc(),
-     *          TII->get(ARM::BICri))
-     *    .addReg(Addr)            // rD
-     *    .addReg(Addr)            // rN
-     *    .addImm(0xC0000000)      // imm
-     *    .addImm((int64_t) Pred)  // predicate condition
-     *    .addReg(PredReg)         // predicate source register (CPSR)
-     *    .addReg(0);              // flag output register (0 == no flags)
-     */
-  }
-}
-
-static bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
-  unsigned Opcode = MI.getOpcode();
-  switch (Opcode) {
-  default: return false;
-
-  // Instructions with base address register in position 0...
-  case ARM::STMIA:
-  case ARM::STMDA:
-  case ARM::STMDB:
-  case ARM::STMIB:
-
-  case ARM::VSTMDIA:
-  case ARM::VSTMSIA:
-    *AddrIdx = 0;
-    break;
-
-  // Instructions with base address register in position 1...
-  case ARM::STMIA_UPD: // same reg at position 0 and position 1
-  case ARM::STMDA_UPD:
-  case ARM::STMDB_UPD:
-  case ARM::STMIB_UPD:
-
-  case ARM::STRH:
-  case ARM::STRi12:
-  case ARM::STRrs:
-  case ARM::STRBi12:
-  case ARM::STRBrs:
-  case ARM::VSTMDIA_UPD:
-  case ARM::VSTMDDB_UPD:
-  case ARM::VSTMSIA_UPD:
-  case ARM::VSTMSDB_UPD:
-  case ARM::VSTRS:
-  case ARM::VSTRD:
-    *AddrIdx = 1;
-    break;
 
   //
   // NEON loads
@@ -854,6 +760,100 @@ static bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
   case ARM::VLD4DUPq32_UPD:
     *AddrIdx = 5;
     break;
+  }
+
+  if (MI.getOperand(*AddrIdx).getReg() == ARM::SP) {
+    // The contents of SP do not require masking.
+    return false;
+  }
+
+  return true;
+}
+
+/*
+ * Sandboxes a memory reference instruction by inserting an appropriate mask
+ * or check operation before it.
+ */
+void ARMNaClRewritePass::SandboxMemory(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator MBBI,
+                                       MachineInstr &MI,
+                                       int AddrIdx,
+                                       bool IsLoad) {
+  unsigned Addr = MI.getOperand(AddrIdx).getReg();
+
+  if (!FlagNaClUseM23ArmAbi && Addr == ARM::R9) {
+    // R9-relative loads are no longer sandboxed.
+    assert(IsLoad && "There should be no r9-relative stores");
+  } else {
+    unsigned Opcode;
+    if (IsLoad && (MI.getOperand(0).getReg() == ARM::SP)) {
+      Opcode = ARM::SFI_GUARD_SP_LOAD;
+    } else {
+      Opcode = ARM::SFI_GUARD_LOADSTORE;
+    }
+    // Use same predicate as current instruction.
+    unsigned PredReg = 0;
+    ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
+    // Use the older BIC sandbox, which is universal, but incurs a stall.
+    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode))
+      .addReg(Addr, RegState::Define)  // Address definition (as dst).
+      .addReg(Addr, RegState::Kill)    // Address read (as src).
+      .addImm((int64_t) Pred)          // predicate condition
+      .addReg(PredReg);                // predicate source register (CPSR)
+
+    /*
+     * This pseudo-instruction is intended to generate something resembling the
+     * following, but with alignment enforced.
+     * TODO(cbiffle): move alignment into this function, use the code below.
+     *
+     *  // bic<cc> Addr, Addr, #0xC0000000
+     *  BuildMI(MBB, MBBI, MI.getDebugLoc(),
+     *          TII->get(ARM::BICri))
+     *    .addReg(Addr)            // rD
+     *    .addReg(Addr)            // rN
+     *    .addImm(0xC0000000)      // imm
+     *    .addImm((int64_t) Pred)  // predicate condition
+     *    .addReg(PredReg)         // predicate source register (CPSR)
+     *    .addReg(0);              // flag output register (0 == no flags)
+     */
+  }
+}
+
+static bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
+  unsigned Opcode = MI.getOpcode();
+  switch (Opcode) {
+  default: return false;
+
+  // Instructions with base address register in position 0...
+  case ARM::STMIA:
+  case ARM::STMDA:
+  case ARM::STMDB:
+  case ARM::STMIB:
+
+  case ARM::VSTMDIA:
+  case ARM::VSTMSIA:
+    *AddrIdx = 0;
+    break;
+
+  // Instructions with base address register in position 1...
+  case ARM::STMIA_UPD: // same reg at position 0 and position 1
+  case ARM::STMDA_UPD:
+  case ARM::STMDB_UPD:
+  case ARM::STMIB_UPD:
+
+  case ARM::STRH:
+  case ARM::STRi12:
+  case ARM::STRrs:
+  case ARM::STRBi12:
+  case ARM::STRBrs:
+  case ARM::VSTMDIA_UPD:
+  case ARM::VSTMDDB_UPD:
+  case ARM::VSTMSIA_UPD:
+  case ARM::VSTMSDB_UPD:
+  case ARM::VSTRS:
+  case ARM::VSTRD:
+    *AddrIdx = 1;
+    break;
 
   //
   // NEON stores
diff --git a/test/NaCl/ARM/neon-vld3-sandboxing.ll b/test/NaCl/ARM/neon-vld3-sandboxing.ll
index 749a913fd4..7fb8eb3077 100644
--- a/test/NaCl/ARM/neon-vld3-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld3-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 %struct.__neon_int8x8x3_t = type { <8 x i8>,  <8 x i8>,  <8 x i8> }
diff --git a/test/NaCl/ARM/neon-vld4-sandboxing.ll b/test/NaCl/ARM/neon-vld4-sandboxing.ll
index 4393998fc6..570a3ce24c 100644
--- a/test/NaCl/ARM/neon-vld4-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vld4-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
diff --git a/test/NaCl/ARM/neon-vlddup-sandboxing.ll b/test/NaCl/ARM/neon-vlddup-sandboxing.ll
index cd77ace644..18e1b41de1 100644
--- a/test/NaCl/ARM/neon-vlddup-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vlddup-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
diff --git a/test/NaCl/ARM/neon-vldlane-sandboxing.ll b/test/NaCl/ARM/neon-vldlane-sandboxing.ll
index 716da93298..fbcef81ac9 100644
--- a/test/NaCl/ARM/neon-vldlane-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vldlane-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 %struct.__neon_int8x8x2_t = type { <8 x i8>,  <8 x i8> }
diff --git a/test/NaCl/ARM/neon-vst1-sandboxing.ll b/test/NaCl/ARM/neon-vst1-sandboxing.ll
index ec5712ee94..4c472aa216 100644
--- a/test/NaCl/ARM/neon-vst1-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vst1-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
@@ -101,6 +101,7 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
+; CHECK:         bic r1, r1, #3221225472
   %A = load float** %ptr
   %tmp0 = bitcast float* %A to i8*
   %tmp1 = load <2 x float>* %B
diff --git a/test/NaCl/ARM/neon-vst2-sandboxing.ll b/test/NaCl/ARM/neon-vst2-sandboxing.ll
index 431f68612c..f01064f877 100644
--- a/test/NaCl/ARM/neon-vst2-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vst2-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
@@ -81,6 +81,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
+; CHECK:         bic r1, r1, #3221225472
   %A = load i8** %ptr
   %tmp1 = load <8 x i8>* %B
   call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
diff --git a/test/NaCl/ARM/neon-vst3-sandboxing.ll b/test/NaCl/ARM/neon-vst3-sandboxing.ll
index 95f85bbeb6..856f728f16 100644
--- a/test/NaCl/ARM/neon-vst3-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vst3-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
diff --git a/test/NaCl/ARM/neon-vst4-sandboxing.ll b/test/NaCl/ARM/neon-vst4-sandboxing.ll
index 2b0eb31b3d..550de7dd72 100644
--- a/test/NaCl/ARM/neon-vst4-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vst4-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
diff --git a/test/NaCl/ARM/neon-vstlane-sandboxing.ll b/test/NaCl/ARM/neon-vstlane-sandboxing.ll
index 8da70115f9..769a7c6712 100644
--- a/test/NaCl/ARM/neon-vstlane-sandboxing.ll
+++ b/test/NaCl/ARM/neon-vstlane-sandboxing.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -filetype=obj %s -o - \
+; RUN: llc -mtriple=armv7-unknown-nacl -mattr=+neon -sfi-store -sfi-load -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
 
 define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
@@ -196,6 +196,7 @@ declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
+; CHECK:         bic r1, r1, #3221225472
   %A = load i16** %ptr
   %tmp0 = bitcast i16* %A to i8*
   %tmp1 = load <4 x i16>* %B