add double <-> int conversion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30858 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 40 insertions, 2 deletions

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index c27136c473..f219b2aadd 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -49,6 +49,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
 
   setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
 
+  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
 
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
@@ -96,8 +97,10 @@ namespace llvm {
       BR,
 
       FSITOS,
+      FTOSIS,
 
       FSITOD,
+      FTOSID,
 
       FUITOS,
 
@@ -148,7 +151,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::CMP:           return "ARMISD::CMP";
   case ARMISD::BR:            return "ARMISD::BR";
   case ARMISD::FSITOS:        return "ARMISD::FSITOS";
+  case ARMISD::FTOSIS:        return "ARMISD::FTOSIS";
   case ARMISD::FSITOD:        return "ARMISD::FSITOD";
+  case ARMISD::FTOSID:        return "ARMISD::FTOSID";
   case ARMISD::FUITOS:        return "ARMISD::FUITOS";
   case ARMISD::FUITOD:        return "ARMISD::FUITOD";
   case ARMISD::FMRRD:         return "ARMISD::FMRRD";
@@ -586,6 +591,17 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(op, vt, Tmp);
 }
 
+static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+  assert(Op.getValueType() == MVT::i32);
+  SDOperand FloatVal = Op.getOperand(0);
+  MVT::ValueType  vt = FloatVal.getValueType();
+  assert(vt == MVT::f32 || vt == MVT::f64);
+
+  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID;
+  SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
+  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
+}
+
 static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   SDOperand IntVal  = Op.getOperand(0);
   assert(IntVal.getValueType() == MVT::i32);
@@ -607,6 +623,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return LowerConstantPool(Op, DAG);
   case ISD::GlobalAddress:
     return LowerGlobalAddress(Op, DAG);
+  case ISD::FP_TO_SINT:
+    return LowerFP_TO_SINT(Op, DAG);
   case ISD::SINT_TO_FP:
     return LowerSINT_TO_FP(Op, DAG);
   case ISD::UINT_TO_FP:
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 45728ac607..13153dedc3 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -77,7 +77,9 @@ def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
 def armfsitos      : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armftosis      : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
 def armfsitod      : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
+def armftosid      : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
 def armfuitos      : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
 def armfuitod      : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
 
@@ -201,9 +203,15 @@ def FMDRR   : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
 def FSITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
 
+def FTOSIS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+                       "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
+
 def FSITOD  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
                        "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
 
+def FTOSID  : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+                       "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
+
 def FUITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
 
diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll
index 310a1150d7..c20cf62f6a 100644
--- a/test/CodeGen/ARM/fpconv.ll
+++ b/test/CodeGen/ARM/fpconv.ll
@@ -2,14 +2,26 @@
 ; RUN: llvm-as < %s | llc -march=arm | grep fcvtds &&
 ; RUN: llvm-as < %s | llc -march=arm | grep fcvtsd
 
-float %f(double %x) {
+float %f1(double %x) {
 entry:
 	%tmp1 = cast double %x to float
 	ret float %tmp1
 }
 
-double %g(float %x) {
+double %f2(float %x) {
 entry:
 	%tmp1 = cast float %x to double
 	ret double %tmp1
 }
+
+int %f3(float %x) {
+entry:
+        %tmp = cast float %x to int
+        ret int %tmp
+}
+
+int %f4(double %x) {
+entry:
+        %tmp = cast double %x to int
+        ret int %tmp
+}