Revamp the Register class, and allow the use of the RegisterGroup class to

specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 158 insertions, 129 deletions

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 58be140eea..b741a2a843 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -10,64 +10,84 @@
 //
 //===----------------------------------------------------------------------===//
 
-class PPCReg : Register {
+class PPCReg<string n> : Register<n> {
   let Namespace = "PPC";
 }
 
 // We identify all our registers with a 5-bit ID, for consistency's sake.
 
 // GPR - One of the 32 32-bit general-purpose registers
-class GPR<bits<5> num> : PPCReg {
+class GPR<bits<5> num, string n> : PPCReg<n> {
   field bits<5> Num = num;
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<5> num> : PPCReg {
+class SPR<bits<5> num, string n> : PPCReg<n> {
   field bits<5> Num = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
-class FPR<bits<5> num> : PPCReg {
+class FPR<bits<5> num, string n> : PPCReg<n> {
   field bits<5> Num = num;
 }
 
 // CR - One of the 8 4-bit condition registers
-class CR<bits<5> num> : PPCReg {
+class CR<bits<5> num, string n> : PPCReg<n> {
   field bits<5> Num = num;
 }
 
 // General-purpose registers
-def R0  : GPR< 0>;  def R1  : GPR< 1>;  def R2  : GPR< 2>;  def R3  : GPR< 3>;
-def R4  : GPR< 4>;  def R5  : GPR< 5>;  def R6  : GPR< 6>;  def R7  : GPR< 7>;
-def R8  : GPR< 8>;  def R9  : GPR< 9>;  def R10 : GPR<10>;  def R11 : GPR<11>;
-def R12 : GPR<12>;  def R13 : GPR<13>;  def R14 : GPR<14>;  def R15 : GPR<15>;
-def R16 : GPR<16>;  def R17 : GPR<17>;  def R18 : GPR<18>;  def R19 : GPR<19>;
-def R20 : GPR<20>;  def R21 : GPR<21>;  def R22 : GPR<22>;  def R23 : GPR<23>;
-def R24 : GPR<24>;  def R25 : GPR<25>;  def R26 : GPR<26>;  def R27 : GPR<27>;
-def R28 : GPR<28>;  def R29 : GPR<29>;  def R30 : GPR<30>;  def R31 : GPR<31>;
+def R0  : GPR< 0,  "R0">;  def R1  : GPR< 1,  "R1">;
+def R2  : GPR< 2,  "R2">;  def R3  : GPR< 3,  "R3">;
+def R4  : GPR< 4,  "R4">;  def R5  : GPR< 5,  "R5">;
+def R6  : GPR< 6,  "R6">;  def R7  : GPR< 7,  "R7">;
+def R8  : GPR< 8,  "R8">;  def R9  : GPR< 9,  "R9">;
+def R10 : GPR<10, "R10">;  def R11 : GPR<11, "R11">;
+def R12 : GPR<12, "R12">;  def R13 : GPR<13, "R13">;
+def R14 : GPR<14, "R14">;  def R15 : GPR<15, "R15">;
+def R16 : GPR<16, "R16">;  def R17 : GPR<17, "R17">;
+def R18 : GPR<18, "R18">;  def R19 : GPR<19, "R19">;
+def R20 : GPR<20, "R20">;  def R21 : GPR<21, "R21">;
+def R22 : GPR<22, "R22">;  def R23 : GPR<23, "R23">;
+def R24 : GPR<24, "R24">;  def R25 : GPR<25, "R25">;
+def R26 : GPR<26, "R26">;  def R27 : GPR<27, "R27">;
+def R28 : GPR<28, "R28">;  def R29 : GPR<29, "R29">;
+def R30 : GPR<30, "R30">;  def R31 : GPR<31, "R31">;
 
 // Floating-point registers
-def F0  : FPR< 0>;  def F1  : FPR< 1>;  def F2  : FPR< 2>;  def F3  : FPR< 3>;
-def F4  : FPR< 4>;  def F5  : FPR< 5>;  def F6  : FPR< 6>;  def F7  : FPR< 7>;
-def F8  : FPR< 8>;  def F9  : FPR< 9>;  def F10 : FPR<10>;  def F11 : FPR<11>;
-def F12 : FPR<12>;  def F13 : FPR<13>;  def F14 : FPR<14>;  def F15 : FPR<15>;
-def F16 : FPR<16>;  def F17 : FPR<17>;  def F18 : FPR<18>;  def F19 : FPR<19>;
-def F20 : FPR<20>;  def F21 : FPR<21>;  def F22 : FPR<22>;  def F23 : FPR<23>;
-def F24 : FPR<24>;  def F25 : FPR<25>;  def F26 : FPR<26>;  def F27 : FPR<27>;
-def F28 : FPR<28>;  def F29 : FPR<29>;  def F30 : FPR<30>;  def F31 : FPR<31>;
+def F0  : FPR< 0,  "F0">;  def F1  : FPR< 1,  "F1">;
+def F2  : FPR< 2,  "F2">;  def F3  : FPR< 3,  "F3">;
+def F4  : FPR< 4,  "F4">;  def F5  : FPR< 5,  "F5">;
+def F6  : FPR< 6,  "F6">;  def F7  : FPR< 7,  "F7">;
+def F8  : FPR< 8,  "F8">;  def F9  : FPR< 9,  "F9">;
+def F10 : FPR<10, "F10">;  def F11 : FPR<11, "F11">;
+def F12 : FPR<12, "F12">;  def F13 : FPR<13, "F13">;
+def F14 : FPR<14, "F14">;  def F15 : FPR<15, "F15">;
+def F16 : FPR<16, "F16">;  def F17 : FPR<17, "F17">;
+def F18 : FPR<18, "F18">;  def F19 : FPR<19, "F19">;
+def F20 : FPR<20, "F20">;  def F21 : FPR<21, "F21">;
+def F22 : FPR<22, "F22">;  def F23 : FPR<23, "F23">;
+def F24 : FPR<24, "F24">;  def F25 : FPR<25, "F25">;
+def F26 : FPR<26, "F26">;  def F27 : FPR<27, "F27">;
+def F28 : FPR<28, "F28">;  def F29 : FPR<29, "F29">;
+def F30 : FPR<30, "F30">;  def F31 : FPR<31, "F31">;
+
 
 // Condition registers
-def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
-def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
+def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">;
+def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">;
+def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">;
+def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">;
 
 // Floating-point status and control register
-def FPSCR : SPR<0>;
+def FPSCR : SPR<0, "FPSCR">;
 // fiXed-point Exception Register? :-)
-def XER : SPR<1>;
+def XER : SPR<1, "XER">;
 // Link register
-def LR : SPR<2>;
+def LR : SPR<2,   "LR">;
 // Count register
-def CTR : SPR<3>;
+def CTR : SPR<3, "CTR">;
 // These are the "time base" registers which are read-only in user mode.
-def TBL : SPR<4>;
-def TBU : SPR<5>;
+def TBL : SPR<4, "TBL">;
+def TBU : SPR<5, "TBU">;
+
diff --git a/lib/Target/Skeleton/SkeletonRegisterInfo.td b/lib/Target/Skeleton/SkeletonRegisterInfo.td
index b8b1bb20d2..901502d379 100644
--- a/lib/Target/Skeleton/SkeletonRegisterInfo.td
+++ b/lib/Target/Skeleton/SkeletonRegisterInfo.td
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-class SkelReg : Register {
+class SkelReg<string n> : Register<n> {
   let Namespace = "Skeleton";
 }
 
@@ -20,60 +20,79 @@ class SkelReg : Register {
 
 
 // GPR - One of the 32 32-bit general-purpose registers
-class GPR<bits<5> num> : SkelReg {
+class GPR<bits<5> num, string n> : SkelReg<n> {
   field bits<5> Num = num;
 }
 
 // SPR - One of the 32-bit special-purpose registers
-class SPR<bits<5> num> : SkelReg {
+class SPR<bits<5> num, string n> : SkelReg<n> {
   field bits<5> Num = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
-class FPR<bits<5> num> : SkelReg {
+class FPR<bits<5> num, string n> : SkelReg<n> {
   field bits<5> Num = num;
 }
 
 // CR - One of the 8 4-bit condition registers
-class CR<bits<5> num> : SkelReg {
+class CR<bits<5> num, string n> : SkelReg<n> {
   field bits<5> Num = num;
 }
 
 // General-purpose registers
-def R0  : GPR< 0>;  def R1  : GPR< 1>;  def R2  : GPR< 2>;  def R3  : GPR< 3>;
-def R4  : GPR< 4>;  def R5  : GPR< 5>;  def R6  : GPR< 6>;  def R7  : GPR< 7>;
-def R8  : GPR< 8>;  def R9  : GPR< 9>;  def R10 : GPR<10>;  def R11 : GPR<11>;
-def R12 : GPR<12>;  def R13 : GPR<13>;  def R14 : GPR<14>;  def R15 : GPR<15>;
-def R16 : GPR<16>;  def R17 : GPR<17>;  def R18 : GPR<18>;  def R19 : GPR<19>;
-def R20 : GPR<20>;  def R21 : GPR<21>;  def R22 : GPR<22>;  def R23 : GPR<23>;
-def R24 : GPR<24>;  def R25 : GPR<25>;  def R26 : GPR<26>;  def R27 : GPR<27>;
-def R28 : GPR<28>;  def R29 : GPR<29>;  def R30 : GPR<30>;  def R31 : GPR<31>;
+def R0  : GPR< 0,  "R0">;  def R1  : GPR< 1,  "R1">;
+def R2  : GPR< 2,  "R2">;  def R3  : GPR< 3,  "R3">;
+def R4  : GPR< 4,  "R4">;  def R5  : GPR< 5,  "R5">;
+def R6  : GPR< 6,  "R6">;  def R7  : GPR< 7,  "R7">;
+def R8  : GPR< 8,  "R8">;  def R9  : GPR< 9,  "R9">;
+def R10 : GPR<10, "R10">;  def R11 : GPR<11, "R11">;
+def R12 : GPR<12, "R12">;  def R13 : GPR<13, "R13">;
+def R14 : GPR<14, "R14">;  def R15 : GPR<15, "R15">;
+def R16 : GPR<16, "R16">;  def R17 : GPR<17, "R17">;
+def R18 : GPR<18, "R18">;  def R19 : GPR<19, "R19">;
+def R20 : GPR<20, "R20">;  def R21 : GPR<21, "R21">;
+def R22 : GPR<22, "R22">;  def R23 : GPR<23, "R23">;
+def R24 : GPR<24, "R24">;  def R25 : GPR<25, "R25">;
+def R26 : GPR<26, "R26">;  def R27 : GPR<27, "R27">;
+def R28 : GPR<28, "R28">;  def R29 : GPR<29, "R29">;
+def R30 : GPR<30, "R30">;  def R31 : GPR<31, "R31">;
 
 // Floating-point registers
-def F0  : FPR< 0>;  def F1  : FPR< 1>;  def F2  : FPR< 2>;  def F3  : FPR< 3>;
-def F4  : FPR< 4>;  def F5  : FPR< 5>;  def F6  : FPR< 6>;  def F7  : FPR< 7>;
-def F8  : FPR< 8>;  def F9  : FPR< 9>;  def F10 : FPR<10>;  def F11 : FPR<11>;
-def F12 : FPR<12>;  def F13 : FPR<13>;  def F14 : FPR<14>;  def F15 : FPR<15>;
-def F16 : FPR<16>;  def F17 : FPR<17>;  def F18 : FPR<18>;  def F19 : FPR<19>;
-def F20 : FPR<20>;  def F21 : FPR<21>;  def F22 : FPR<22>;  def F23 : FPR<23>;
-def F24 : FPR<24>;  def F25 : FPR<25>;  def F26 : FPR<26>;  def F27 : FPR<27>;
-def F28 : FPR<28>;  def F29 : FPR<29>;  def F30 : FPR<30>;  def F31 : FPR<31>;
+def F0  : FPR< 0,  "F0">;  def F1  : FPR< 1,  "F1">;
+def F2  : FPR< 2,  "F2">;  def F3  : FPR< 3,  "F3">;
+def F4  : FPR< 4,  "F4">;  def F5  : FPR< 5,  "F5">;
+def F6  : FPR< 6,  "F6">;  def F7  : FPR< 7,  "F7">;
+def F8  : FPR< 8,  "F8">;  def F9  : FPR< 9,  "F9">;
+def F10 : FPR<10, "F10">;  def F11 : FPR<11, "F11">;
+def F12 : FPR<12, "F12">;  def F13 : FPR<13, "F13">;
+def F14 : FPR<14, "F14">;  def F15 : FPR<15, "F15">;
+def F16 : FPR<16, "F16">;  def F17 : FPR<17, "F17">;
+def F18 : FPR<18, "F18">;  def F19 : FPR<19, "F19">;
+def F20 : FPR<20, "F20">;  def F21 : FPR<21, "F21">;
+def F22 : FPR<22, "F22">;  def F23 : FPR<23, "F23">;
+def F24 : FPR<24, "F24">;  def F25 : FPR<25, "F25">;
+def F26 : FPR<26, "F26">;  def F27 : FPR<27, "F27">;
+def F28 : FPR<28, "F28">;  def F29 : FPR<29, "F29">;
+def F30 : FPR<30, "F30">;  def F31 : FPR<31, "F31">;
+
 
 // Condition registers
-def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
-def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
+def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">;
+def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">;
+def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">;
+def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">;
 
 // Floating-point status and control register
-def FPSCR : SPR<0>;
+def FPSCR : SPR<0, "FPSCR">;
 // fiXed-point Exception Register? :-)
-def XER : SPR<1>;
+def XER : SPR<1, "XER">;
 // Link register
-def LR : SPR<2>;
+def LR : SPR<2,   "LR">;
 // Count register
-def CTR : SPR<3>;
+def CTR : SPR<3, "CTR">;
 // These are the "time base" registers which are read-only in user mode.
-def TBL : SPR<4>;
-def TBU : SPR<5>;
+def TBL : SPR<4, "TBL">;
+def TBU : SPR<5, "TBU">;
 
 /// Register classes: one for floats and another for non-floats.
 ///
diff --git a/lib/Target/SparcV9/SparcV9RegisterInfo.td b/lib/Target/SparcV9/SparcV9RegisterInfo.td
index bea8f033db..3ca88c441d 100644
--- a/lib/Target/SparcV9/SparcV9RegisterInfo.td
+++ b/lib/Target/SparcV9/SparcV9RegisterInfo.td
@@ -12,19 +12,27 @@
 //===----------------------------------------------------------------------===//
 
 // Ri - One of the 32 64 bit integer registers
-class Ri<bits<5> num> : Register {
+class Ri<bits<5> num, string n> : Register<n> {
   field bits<5> Num = num;        // Numbers are identified with a 5 bit ID
 }
 
 let Namespace = "SparcV9" in {
-  def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
-  def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;
-  def O0 : Ri< 8>;    def O1 : Ri< 9>;    def O2 : Ri<10>;    def O3 : Ri<11>;
-  def O4 : Ri<12>;    def O5 : Ri<13>;    def O6 : Ri<14>;    def O7 : Ri<15>;
-  def L0 : Ri<16>;    def L1 : Ri<17>;    def L2 : Ri<18>;    def L3 : Ri<19>;
-  def L4 : Ri<20>;    def L5 : Ri<21>;    def L6 : Ri<22>;    def L7 : Ri<23>;
-  def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
-  def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
+  def G0 : Ri< 0, "G0">;    def G1 : Ri< 1, "G1">;
+  def G2 : Ri< 2, "G2">;    def G3 : Ri< 3, "G3">;
+  def G4 : Ri< 4, "G4">;    def G5 : Ri< 5, "G5">;
+  def G6 : Ri< 6, "G6">;    def G7 : Ri< 7, "G7">;
+  def O0 : Ri< 8, "O0">;    def O1 : Ri< 9, "O1">;
+  def O2 : Ri<10, "O2">;    def O3 : Ri<11, "O3">;
+  def O4 : Ri<12, "O4">;    def O5 : Ri<13, "O5">;
+  def O6 : Ri<14, "O6">;    def O7 : Ri<15, "O7">;
+  def L0 : Ri<16, "L0">;    def L1 : Ri<17, "L1">; 
+  def L2 : Ri<18, "L2">;    def L3 : Ri<19, "L3">;
+  def L4 : Ri<20, "L4">;    def L5 : Ri<21, "L5">;
+  def L6 : Ri<22, "L6">;    def L7 : Ri<23, "L7">;
+  def I0 : Ri<24, "I0">;    def I1 : Ri<25, "I1">;
+  def I2 : Ri<26, "I2">;    def I3 : Ri<27, "I3">;
+  def I4 : Ri<28, "I4">;    def I5 : Ri<29, "I5">;
+  def I6 : Ri<30, "I6">;    def I7 : Ri<31, "I7">;
   // Floating-point registers?
   // ...
 }
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 725d3bd47a..d1f3e7455b 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -43,12 +43,11 @@ def isVoid : ValueType<0  , 11>;   // Produces no value
 // description classes in llvm/Target/MRegisterInfo.h
 
 
-// Register - You should define one instance of this class for each register in
-// the target machine.
-//
-class Register {
+// Register - You should define one instance of this class for each register
+// in the target machine.  String n will become the "name" of the register.
+class RegisterBase<string n> {
   string Namespace = "";
-  string Name = "";
+  string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
   // bits of the spill slot required to hold this register.  If this value is
@@ -62,21 +61,17 @@ class Register {
   int SpillAlignment = 0;
 }
 
-// NamedReg - If the name for the 'def' of the register should not become the
-// "name" of the register, you can use this to specify a custom name instead.
-//
-class NamedReg<string n> : Register {
-  let Name = n;
+class Register<string n> : RegisterBase<n> {
+  list<RegisterBase> Aliases = [];
 }
 
-// RegisterAliases - You should define instances of this class to indicate which
-// registers in the register file are aliased together.  This allows the code
-// generator to be careful not to put two values with overlapping live ranges
-// into registers which alias.
-//
-class RegisterAliases<Register reg, list<Register> aliases> {
-  Register Reg = reg;
-  list<Register> Aliases = aliases;
+// RegisterGroup - This can be used to define instances of Register which
+// need to specify aliases.
+// List "aliases" specifies which registers are aliased to this one.  This
+// allows the code generator to be careful not to put two values with 
+// overlapping live ranges into registers which alias.
+class RegisterGroup<string n, list<Register> aliases> : Register<n> {
+  let Aliases = aliases;
 }
 
 // RegisterClass - Now that all of the registers are defined, and aliases
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 8e62f90f02..701c7daaa3 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -17,56 +17,46 @@
 //  Register definitions...
 //
 let Namespace = "X86" in {
+
+  // In the register alias definitions below, we define which registers alias
+  // which others.  We only specify which registers the small registers alias,
+  // because the register file generator is smart enough to figure out that
+  // AL aliases AX if we tell it that AX aliased AL (for example).
+
   // 32-bit registers
-  def EAX : Register; def ECX : Register;
-  def EDX : Register; def EBX : Register;
-  def ESP : Register; def EBP : Register;
-  def ESI : Register; def EDI : Register;
+  def EAX : Register<"EAX">; def ECX : Register<"ECX">;
+  def EDX : Register<"EDX">; def EBX : Register<"EBX">;
+  def ESP : Register<"ESP">; def EBP : Register<"EBP">;
+  def ESI : Register<"ESI">; def EDI : Register<"EDI">;
   
   // 16-bit registers
-  def AX : Register; def CX : Register;
-  def DX : Register; def BX : Register;
-  def SP : Register; def BP : Register;
-  def SI : Register; def DI : Register;
+  def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
+  def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
+  def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
+  def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
   
   // 8-bit registers
-  def AL : Register; def CL : Register;
-  def DL : Register; def BL : Register;
-  def AH : Register; def CH : Register;
-  def DH : Register; def BH : Register;
+  def AL : RegisterGroup<"AL", [AX, EAX]>; def CL : RegisterGroup<"CL", [CX, ECX]>;
+  def DL : RegisterGroup<"DL", [DX, EDX]>; def BL : RegisterGroup<"BL", [BX, EBX]>;
+  def AH : RegisterGroup<"AH", [AX, EAX]>; def CH : RegisterGroup<"CH", [CX, ECX]>;
+  def DH : RegisterGroup<"DH", [DX, EDX]>; def BH : RegisterGroup<"BH", [BX, EBX]>;
   
   // Pseudo Floating Point registers
-  def FP0 : Register; def FP1 : Register;
-  def FP2 : Register; def FP3 : Register;
-  def FP4 : Register; def FP5 : Register;
-  def FP6 : Register; 
+  def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
+  def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
+  def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
+  def FP6 : Register<"FP6">; 
 
   // Floating point stack registers
-  def ST0 : NamedReg<"ST(0)">; def ST1 : NamedReg<"ST(1)">;
-  def ST2 : NamedReg<"ST(2)">; def ST3 : NamedReg<"ST(3)">;
-  def ST4 : NamedReg<"ST(4)">; def ST5 : NamedReg<"ST(5)">;
-  def ST6 : NamedReg<"ST(6)">; def ST7 : NamedReg<"ST(7)">; 
+  def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
+  def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
+  def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
+  def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">; 
   
   // Flags, Segment registers, etc...
 }
 
 //===----------------------------------------------------------------------===//
-// Register alias definitions... define which registers alias which others.  We
-// only specify which registers the small registers alias, because the register
-// file generator is smart enough to figure out that AL aliases AX if we tell it
-// that AX aliases AL (for example).
-//
-def : RegisterAliases<AL, [AX, EAX]>; def : RegisterAliases<BL, [BX, EBX]>;
-def : RegisterAliases<CL, [CX, ECX]>; def : RegisterAliases<DL, [DX, EDX]>;
-def : RegisterAliases<AH, [AX, EAX]>; def : RegisterAliases<BH, [BX, EBX]>;
-def : RegisterAliases<CH, [CX, ECX]>; def : RegisterAliases<DH, [DX, EDX]>;
-
-def : RegisterAliases<AX, [EAX]>;     def : RegisterAliases<BX, [EBX]>;
-def : RegisterAliases<CX, [ECX]>;     def : RegisterAliases<DX, [EDX]>;
-def : RegisterAliases<SI, [ESI]>;     def : RegisterAliases<DI, [EDI]>;
-def : RegisterAliases<SP, [ESP]>;     def : RegisterAliases<BP, [EBP]>;
-
-//===----------------------------------------------------------------------===//
 // Register Class Definitions... now that we have all of the pieces, define the
 // top-level register classes.  The order specified in the register list is
 // implicitly defined to be the register allocation order.
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 487890d374..e37442b1c9 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -139,15 +139,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
   OS << "  };\n";
 
   // Emit register class aliases...
-  std::vector<Record*> RegisterAliasesRecs =
-    Records.getAllDerivedDefinitions("RegisterAliases");
   std::map<Record*, std::set<Record*> > RegisterAliases;
+  const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
 
-  for (unsigned i = 0, e = RegisterAliasesRecs.size(); i != e; ++i) {
-    Record *AS = RegisterAliasesRecs[i];
-    Record *R = AS->getValueAsDef("Reg");
-    ListInit *LI = AS->getValueAsListInit("Aliases");
-
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    Record *R = Regs[i].TheDef;
+    ListInit *LI = Regs[i].TheDef->getValueAsListInit("Aliases");
     // Add information that R aliases all of the elements in the list... and
     // that everything in the list aliases R.
     for (unsigned j = 0, e = LI->getSize(); j != e; ++j) {
@@ -165,7 +162,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
                   << " specified multiple times!\n";
       RegisterAliases[Reg->getDef()].insert(R);
     }
-  }
+  } 
 
   if (!RegisterAliases.empty())
     OS << "\n\n  // Register Alias Sets...\n";