diff options
| author | Craig Topper <craig.topper@gmail.com> | 2012-01-01 19:51:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-01-01 19:51:58 +0000 |
| commit | a86bcfb565bdea5bd45634fd2139ac17172a3500 (patch) | |
| tree | 925e3e54711c0431cdee7b0c7ce19690ba1b8911 | |
| parent | de9e4c728e9016d8d701c2e78a96647fbb98779a (diff) | |
Allow CRC32 instructions to be selected when AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-intrinsics-x86.ll | 21 |
3 files changed, 24 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 2da9b4baeb..dc92cb53ce 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -436,8 +436,8 @@ class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, // SS42FI - SSE 4.2 instructions with T8XD prefix. class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> - : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>; - + : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42orAVX]>; + // SS42AI = SSE 4.2 instructions with TA prefix class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index fe83ae9ddd..7af8507ce8 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -476,6 +476,7 @@ def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; def HasXMM : Predicate<"Subtarget->hasXMM()">; def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">; def HasSSE3orAVX : Predicate<"Subtarget->hasSSE3orAVX()">; +def HasSSE42orAVX : Predicate<"Subtarget->hasSSE42orAVX()">; def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; def HasAES : Predicate<"Subtarget->hasAES()">; diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index b4f04ceb8f..f980a6ac39 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -2530,3 +2530,24 @@ entry: ret void } declare void @llvm.x86.sse2.clflush(i8*) nounwind + +; CHECK: crc32b +define i32 @crc32_32_8(i32 %a, i8 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b) + ret i32 %tmp +} +declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind + +; CHECK: crc32w +define i32 @crc32_32_16(i32 %a, i16 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b) + ret i32 %tmp +} +declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind + +; CHECK: crc32l +define i32 @crc32_32_32(i32 %a, i32 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b) + ret i32 %tmp +} +declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind |