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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-01 18:15:06 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-01 18:15:06 +0000 |
| commit | a39ccdb9d4829548756efaaac0d19ebae8b7ff5d (patch) | |
| tree | 05ee8b89c3b1b0c1196bd23e331bfba2be56cd9a | |
| parent | c047dcade506a5acaccb1548cb83a3f85f52d71d (diff) | |
Fix vbroadcast matching logic to early unmatch if the node doesn't have
only one use. Fix PR10825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138951 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-vbroadcast.ll | 10 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 0d45414930..706b1a2f80 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6409,12 +6409,16 @@ static bool isVectorBroadcast(SDValue &Op) { if (Is256) V = V.getOperand(1); - if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR) + + if (!V.hasOneUse()) return false; // Check the source scalar_to_vector type. 256-bit broadcasts are // supported for 32/64-bit sizes, while 128-bit ones are only supported // for 32-bit scalars. + if (V.getOpcode() != ISD::SCALAR_TO_VECTOR) + return false; + unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits(); if (ScalarSize != 32 && ScalarSize != 64) return false; diff --git a/test/CodeGen/X86/avx-vbroadcast.ll b/test/CodeGen/X86/avx-vbroadcast.ll index ffa9710677..89b4188440 100644 --- a/test/CodeGen/X86/avx-vbroadcast.ll +++ b/test/CodeGen/X86/avx-vbroadcast.ll @@ -75,6 +75,7 @@ entry: ; CHECK: _G ; CHECK-NOT: vbroadcastsd (% +; CHECK: ret define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp { entry: %q = load i64* %ptr, align 8 @@ -82,3 +83,12 @@ entry: %vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1 ret <2 x i64> %vecinit2.i } + +; CHECK: _H +; CHECK-NOT: vbroadcastss +; CHECK: ret +define <4 x i32> @H(<4 x i32> %a) { + %x = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> + ret <4 x i32> %x +} + |