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| author | Devang Patel <dpatel@apple.com> | 2012-01-27 19:48:28 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2012-01-27 19:48:28 +0000 |
| commit | a28101e61aa3aeed5baf3d5b91d0f8bcb4e9e12a (patch) | |
| tree | fdfe858b1789520f3b7652875a239b1834f5fa94 | |
| parent | a21bb20f5943f5f4c66d4727784c26007db2470c (diff) | |
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/AsmParser/X86AsmParser.cpp | 8 | ||||
| -rw-r--r-- | test/MC/X86/intel-syntax.s | 2 |
2 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 3afdaf2d75..266f521b70 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -610,7 +610,6 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, // Parse BaseReg if (ParseRegister(BaseReg, Start, End)) { // Handle '[' 'symbol' ']' - const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext()); if (getParser().ParseExpression(Disp, End)) return 0; if (getLexer().isNot(AsmToken::RBrac)) return ErrorOperand(Start, "Expected ']' token!"); @@ -624,8 +623,11 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, if (getLexer().is(AsmToken::RBrac)) { // Handle '[' number ']' Parser.Lex(); - return X86Operand::CreateMem(MCConstantExpr::Create(Val, getContext()), - Start, End, Size); + const MCExpr *Disp = MCConstantExpr::Create(Val, getContext()); + if (SegReg) + return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale, + Start, End, Size); + return X86Operand::CreateMem(Disp, Start, End, Size); } else if (getLexer().is(AsmToken::Star)) { // Handle '[' Scale*IndexReg ']' Parser.Lex(); diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s index 2c69280711..7cd56777b0 100644 --- a/test/MC/X86/intel-syntax.s +++ b/test/MC/X86/intel-syntax.s @@ -61,4 +61,6 @@ _main: lea R8D, DWORD PTR [4*RDI] // CHECK: movl _fnan(,%ecx,4), %ecx mov ECX, DWORD PTR [4*ECX + _fnan] +// CHECK: movq %fs:320, %rax + mov RAX, QWORD PTR FS:[320] ret |