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authorDaniel Dunbar <daniel@zuster.org>2010-07-19 07:21:07 +0000
committerDaniel Dunbar <daniel@zuster.org>2010-07-19 07:21:07 +0000
commit926f2bb3d8dd6f8b0198aa478828ee02914050f9 (patch)
tree3f284506f6a57d63a050e21f3b86d4e1690d2471
parente4c52a2c41a63b424ac8ce22adc833f35b23e18d (diff)
X86-64: Mark WINCALL and more tail call instructions as code gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86Instr64bit.td5
-rw-r--r--test/MC/AsmParser/X86/x86_instructions.s2
2 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 9baba5d072..0b4cd98ef0 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -158,7 +158,7 @@ let isCall = 1 in
// FIXME: We need to teach codegen about single list of call-clobbered
// registers.
-let isCall = 1 in
+let isCall = 1, isCodeGenOnly = 1 in
// All calls clobber the non-callee saved registers. RSP is marked as
// a use to prevent stack-pointer assignments that appear immediately
// before calls from potentially appearing dead. Uses for argument
@@ -182,7 +182,8 @@ let isCall = 1 in
}
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+ isCodeGenOnly = 1 in
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s
index 4bc8a4bb3a..92fb1b2431 100644
--- a/test/MC/AsmParser/X86/x86_instructions.s
+++ b/test/MC/AsmParser/X86/x86_instructions.s
@@ -56,7 +56,7 @@
subl %eax, %ebx
// FIXME: Check that this matches the correct instruction.
-// CHECK: call *%rax
+// CHECK: callq *%rax
call *%rax
// FIXME: Check that this matches the correct instruction.