Make it compile

12 files changed, 123 insertions, 13 deletions

diff --git a/lib/Linker/LinkModules.cpp b/lib/Linker/LinkModules.cpp
index 156b536353..a7a1cc2b94 100644
--- a/lib/Linker/LinkModules.cpp
+++ b/lib/Linker/LinkModules.cpp
@@ -20,6 +20,7 @@
 #include "llvm/IR/Module.h"
 #include "llvm/IR/TypeFinder.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Path.h"           // @LOCALMOD
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Utils/Cloning.h"
 using namespace llvm;
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 063043f51b..ce0c6996ec 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1654,6 +1654,41 @@ multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
 // Instructions
 //===----------------------------------------------------------------------===//
 
+// @LOCALMOD-START
+
+def SFI_GUARD_LOADSTORE :
+PseudoInst<(outs GPR:$dst), (ins GPR:$a, pred:$p), NoItinerary, []>;
+
+let Defs = [CPSR] in
+def SFI_GUARD_LOADSTORE_TST :
+PseudoInst<(outs), (ins GPR:$a), NoItinerary, []>;
+
+// Like SFI_GUARD_LOADSTORE, but reserved for loads into SP.
+def SFI_GUARD_SP_LOAD :
+PseudoInst<(outs GPR:$dst), (ins GPR:$src, pred:$p), NoItinerary, []>;
+
+def SFI_GUARD_INDIRECT_CALL :
+PseudoInst<(outs GPR:$dst), (ins GPR:$a, pred:$p), NoItinerary, []>;
+
+def SFI_GUARD_INDIRECT_JMP :
+PseudoInst<(outs GPR:$dst), (ins GPR:$a, pred:$p), NoItinerary, []>;
+
+def SFI_GUARD_CALL :
+PseudoInst<(outs), (ins pred:$p), NoItinerary, []>;
+
+// NOTE: the BX_RET instruction hardcodes lr as well
+def SFI_GUARD_RETURN :
+PseudoInst<(outs), (ins pred:$p), NoItinerary, []>;
+
+def SFI_NOP_IF_AT_BUNDLE_END :
+PseudoInst<(outs), (ins), NoItinerary, []>;
+
+// Note: intention is that $src and $dst are the same register.
+def SFI_DATA_MASK :
+PseudoInst<(outs GPR:$dst), (ins GPR:$src, pred:$p), NoItinerary, []>;
+
+// @LOCALMOD-END
+
 //===----------------------------------------------------------------------===//
 //  Miscellaneous Instructions.
 //
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 48fd903f80..b0e2f182b9 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -27,7 +27,8 @@
 
 using namespace llvm;
 
-static cl::opt<bool>
+// @LOCALMOD: remove 'static' to make this flag visible elsewhere
+cl::opt<bool>
 ReserveR9("arm-reserve-r9", cl::Hidden,
           cl::desc("Reserve R9, making it unavailable as GPR"));
 
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 9be1e454e6..5fd2a82930 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -356,7 +356,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
   else
     setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
   // @LOCALMOD-END
-  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
 
   // Use the default for now
   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
@@ -1557,7 +1556,7 @@ GetNaClThreadPointer(SelectionDAG &DAG, DebugLoc DL) const {
 // @LOCALMOD-END
 
 SDValue MipsTargetLowering::
-LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
+lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
 {
   // If the relocation model is PIC, use the General Dynamic TLS Model or
   // Local Dynamic TLS model, otherwise use the Initial Exec or
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 3169dd075b..e62daba4a1 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -330,7 +330,6 @@ namespace llvm {
                             const SDNode *CallNode, const Type *RetTy) const;
 
     // Lower Operand specifics
-    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; // @LOCALMOD
     SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 057db80e4d..e36980ed0b 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -343,6 +343,85 @@ bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
   return true;
 }
 
+/// @LOCALMOD-BEGIN
+/// isLegalAddressingModeForNaCl - Determine if the addressing mode is
+/// legal for NaCl translation.  If not, the caller is expected to
+/// reject the instruction for fast-ISel code generation.
+///
+/// The logic for the test is translated from the corresponding logic
+/// in X86DAGToDAGISel::LegalizeAddressingModeForNaCl().  It can't be
+/// used directly due to the X86AddressMode vs X86ISelAddressMode
+/// types.  As such, any changes to isLegalAddressingModeForNaCl() and
+/// X86DAGToDAGISel::LegalizeAddressingModeForNaCl() need to be
+/// synchronized.  The original conditions are indicated in comments.
+static bool isLegalAddressingModeForNaCl(const X86Subtarget *Subtarget,
+                                         const X86AddressMode &AM) {
+  if (Subtarget->isTargetNaCl64()) {
+    // Return true (i.e., is legal) if the equivalent of
+    // X86ISelAddressMode::isRIPRelative() is true.
+    if (AM.BaseType == X86AddressMode::RegBase &&
+        AM.Base.Reg == X86::RIP)
+      return true;
+
+    // Check for the equivalent of
+    // (!AM.hasBaseOrIndexReg() &&
+    //  !AM.hasSymbolicDisplacement() &&
+    //  AM.Disp < 0)
+    if (!((AM.BaseType == X86AddressMode::RegBase && AM.Base.Reg) ||
+          AM.IndexReg) &&
+        !AM.GV &&
+        AM.Disp < 0) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // At this point in the LegalizeAddressingModeForNaCl() code, it
+    // normalizes an addressing mode with a base register and no index
+    // register into an equivalent mode with an index register and no
+    // base register.  Since we don't modify AM, we may have to check
+    // both the base and index register fields in the remainder of the
+    // tests.
+
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::FrameIndexBase || AM.GV || AM.CP) &&
+    //   AM.IndexReg.getNode() &&
+    //   AM.Disp > 0)
+    // Note: X86AddressMode doesn't have a CP analogue
+    if ((AM.BaseType == X86AddressMode::FrameIndexBase || AM.GV) &&
+        ((AM.BaseType == X86AddressMode::RegBase && AM.Base.Reg) ||
+         AM.IndexReg) &&
+        AM.Disp > 0) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::RegBase) &&
+    //  AM.Base_Reg.getNode() &&
+    //  AM.IndexReg.getNode())
+    if ((AM.BaseType == X86AddressMode::RegBase) &&
+        AM.Base.Reg &&
+        AM.IndexReg) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // See X86DAGToDAGISel::FoldOffsetIntoAddress().
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::RegBase ||
+    //   AM.BaseType == X86ISelAddressMode::FrameIndexBase) &&
+    //  (Val > 65535 || Val < -65536))
+    if ((AM.BaseType == X86AddressMode::RegBase ||
+         AM.BaseType == X86AddressMode::FrameIndexBase) &&
+        (AM.Disp > 65535 || AM.Disp < -65536)) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+  }
+
+  return true;
+}
+
 /// X86SelectAddress - Attempt to fill in an address from the given value.
 ///
 /// @LOCALMOD-BEGIN
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 28802217fa..a4bbaab155 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1709,9 +1709,6 @@ X86TargetLowering::LowerReturn(SDValue Chain,
            "SRetReturnReg should have been set in LowerFormalArguments().");
     SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
 
-    unsigned RetValReg
-        = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
-          X86::RAX : X86::EAX;
     unsigned RetValReg = Subtarget->isTarget64BitILP32() ? X86::EAX : X86::RAX;
     // @LOCALMOD-BEGIN
     if (Subtarget->isTargetNaCl()) {
diff --git a/tools/llvm-extract/llvm-extract.cpp b/tools/llvm-extract/llvm-extract.cpp
index 8108996996..e18e41ca98 100644
--- a/tools/llvm-extract/llvm-extract.cpp
+++ b/tools/llvm-extract/llvm-extract.cpp
@@ -23,7 +23,6 @@
 #include "llvm/PassManager.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h" // @LOCALMOD
-#include "llvm/Support/IRReader.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Regex.h"
diff --git a/tools/lto/LTOCodeGenerator.cpp b/tools/lto/LTOCodeGenerator.cpp
index 75c718c019..5a597d001d 100644
--- a/tools/lto/LTOCodeGenerator.cpp
+++ b/tools/lto/LTOCodeGenerator.cpp
@@ -150,7 +150,7 @@ bool LTOCodeGenerator::linkGatheredModulesAndDispose(std::string& errMsg) {
   }
 
   // Finally, link Node 0 with the Dest and delete Node 0.
-  if (_linker.LinkInModule(_gatheredModules[0]->getLLVVMModule(), &errMsg)) {
+  if (_linker.linkInModule(_gatheredModules[0]->getLLVVMModule(), &errMsg)) {
     errs() << "LinkModules Dst w/ _gatheredModules[0] failed...\n";
     return true;
   }
diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp
index 1e8fb65e51..a4e3abef91 100644
--- a/tools/opt/opt.cpp
+++ b/tools/opt/opt.cpp
@@ -27,18 +27,18 @@
 #include "llvm/DebugInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Module.h"
-#include "llvm/IRReader/IRReader.h"  // @LOCALMOD
+#include "llvm/IRReader/IRReader.h"
 #include "llvm/LinkAllIR.h"
 #include "llvm/LinkAllPasses.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/IRReader.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PassNameParser.h"
 #include "llvm/Support/PluginLoader.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/SystemUtils.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
diff --git a/tools/pnacl-abicheck/pnacl-abicheck.cpp b/tools/pnacl-abicheck/pnacl-abicheck.cpp
index 8b96f17954..5e4f5b3ae0 100644
--- a/tools/pnacl-abicheck/pnacl-abicheck.cpp
+++ b/tools/pnacl-abicheck/pnacl-abicheck.cpp
@@ -19,7 +19,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/IRReader.h"
+#include "llvm/Support/SourceMgr.h"
 #include <string>
 
 using namespace llvm;
diff --git a/tools/pnacl-llc/pnacl-llc.cpp b/tools/pnacl-llc/pnacl-llc.cpp
index 6292001ab1..42fde81266 100644
--- a/tools/pnacl-llc/pnacl-llc.cpp
+++ b/tools/pnacl-llc/pnacl-llc.cpp
@@ -30,10 +30,10 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/Host.h"
-#include "llvm/Support/IRReader.h"
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/PrettyStackTrace.h"
 #include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/Timer.h"