diff options
| author | Chris Lattner <sabre@nondot.org> | 2004-02-10 20:31:28 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-02-10 20:31:28 +0000 |
| commit | 6d2151871889a4d4c22a0883a8ee667333f1cb0b (patch) | |
| tree | 15127f9c47d432bd438ad63aa3a970f7ffd406f1 | |
| parent | b2e5db94cfb36da77264d9b063e674e907d8458d (diff) | |
Don't use MachineOperator::is(Phys|Virt)Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11276 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/FloatingPoint.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86FloatingPoint.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp index 4231776aee..0a0fe9b2c2 100644 --- a/lib/Target/X86/FloatingPoint.cpp +++ b/lib/Target/X86/FloatingPoint.cpp @@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) { } static unsigned getFPReg(const MachineOperand &MO) { - assert(MO.isPhysicalRegister() && "Expected an FP register!"); + assert(MO.isRegister() && "Expected an FP register!"); unsigned Reg = MO.getReg(); assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); return Reg - X86::FP0; diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 4231776aee..0a0fe9b2c2 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) { } static unsigned getFPReg(const MachineOperand &MO) { - assert(MO.isPhysicalRegister() && "Expected an FP register!"); + assert(MO.isRegister() && "Expected an FP register!"); unsigned Reg = MO.getReg(); assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); return Reg - X86::FP0; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 8911562bfc..298af02d8a 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const { // Make sure the instruction is EXACTLY `xchg ax, ax' if (MI.getOpcode() == X86::XCHGrr16) { const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1); - if (op0.isPhysicalRegister() && op0.getReg() == X86::AX && - op1.isPhysicalRegister() && op1.getReg() == X86::AX) { + if (op0.isRegister() && op0.getReg() == X86::AX && + op1.isRegister() && op1.getReg() == X86::AX) { return true; } } |