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authorNadav Rotem <nadav.rotem@intel.com>2011-09-21 17:14:40 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-09-21 17:14:40 +0000
commit64ac73bb15e510c268479646816ec069ff12cd64 (patch)
tree478a1c9ac9953ee0f7f3c7c947c62c33879a7081
parentd7e0ceaa5984aaaf63d8e12dc888aeb26c930a9f (diff)
fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140258 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index f7aae14bba..36e254b1f5 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -13564,7 +13564,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
// From, To sizes and ElemCount must be pow of two
if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
// We are going to use the original vector elt for storing.
- // accumulated smaller vector elements must be a multiple of the store size.
+ // Accumulated smaller vector elements must be a multiple of the store size.
if (0 != (NumElems * FromSz) % ToSz) return SDValue();
unsigned SizeRatio = FromSz / ToSz;