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| author | Dan Gohman <gohman@apple.com> | 2007-12-14 15:10:00 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2007-12-14 15:10:00 +0000 |
| commit | 1a8001e6652d535b266b6d30e996c41a2b7cc920 (patch) | |
| tree | 0f90d1649c275c927fc92081dcac51910529e1aa | |
| parent | 152804e9c1a9fad358a7a5298cd01d4af0f8cf47 (diff) | |
Fix Intel asm syntax for the bsr and bsf instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45030 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 16 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrX86-64.td | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index a0d72b21ae..2a5e17f356 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -450,32 +450,32 @@ def XCHG32rm : I<0x87, MRMSrcMem, // Bit scan instructions. let Defs = [EFLAGS] in { def BSF16rr : I<0xBC, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), - "bsf{w}\t{$src, $dst||$dst, $src}", + "bsf{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB; def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "bsf{w}\t{$src, $dst||$dst, $src}", + "bsf{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (X86bsf (loadi16 addr:$src))), (implicit EFLAGS)]>, TB; def BSF32rr : I<0xBC, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), - "bsf{l}\t{$src, $dst||$dst, $src}", + "bsf{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB; def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "bsf{l}\t{$src, $dst||$dst, $src}", + "bsf{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (X86bsf (loadi32 addr:$src))), (implicit EFLAGS)]>, TB; def BSR16rr : I<0xBD, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), - "bsr{w}\t{$src, $dst||$dst, $src}", + "bsr{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB; def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "bsr{w}\t{$src, $dst||$dst, $src}", + "bsr{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (X86bsr (loadi16 addr:$src))), (implicit EFLAGS)]>, TB; def BSR32rr : I<0xBD, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), - "bsr{l}\t{$src, $dst||$dst, $src}", + "bsr{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB; def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "bsr{l}\t{$src, $dst||$dst, $src}", + "bsr{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (X86bsr (loadi32 addr:$src))), (implicit EFLAGS)]>, TB; } // Defs = [EFLAGS] diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td index f153c4d7a6..3eb4fd74ef 100644 --- a/lib/Target/X86/X86InstrX86-64.td +++ b/lib/Target/X86/X86InstrX86-64.td @@ -170,17 +170,17 @@ def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), // Bit scan instructions. let Defs = [EFLAGS] in { def BSF64rr : RI<0xBC, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), - "bsf{q}\t{$src, $dst||$dst, $src}", + "bsf{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (X86bsf GR64:$src))]>, TB; def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "bsf{q}\t{$src, $dst||$dst, $src}", + "bsf{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (X86bsf (loadi64 addr:$src)))]>, TB; def BSR64rr : RI<0xBD, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), - "bsr{q}\t{$src, $dst||$dst, $src}", + "bsr{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (X86bsr GR64:$src))]>, TB; def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "bsr{q}\t{$src, $dst||$dst, $src}", + "bsr{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (X86bsr (loadi64 addr:$src)))]>, TB; } // Defs = [EFLAGS] |