Remove the '-disable-scheduling' flag and replace it with the 'source' option of

the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 450 insertions, 696 deletions

diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 5608c999e1..27947e8afe 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -44,6 +44,7 @@ namespace {
       
       (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+      (void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Default);
       (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
       (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index 1cf64a09a7..cf3274f4a9 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -73,6 +73,11 @@ ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
                                                CodeGenOpt::Level OptLevel);
 
+/// createBURRListDAGScheduler - This creates a bottom up register usage
+/// reduction list scheduler that schedules in source code order when possible.
+ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
+                                                 CodeGenOpt::Level OptLevel);
+
 /// createTDListDAGScheduler - This creates a top-down list scheduler with
 /// a hazard recognizer.
 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 1ad7919962..dea5993719 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -46,6 +46,11 @@ static RegisterScheduler
   tdrListrDAGScheduler("list-tdrr",
                        "Top-down register reduction list scheduling",
                        createTDRRListDAGScheduler);
+static RegisterScheduler
+  sourceListDAGScheduler("source",
+                         "Similar to list-burr but schedules in source "
+                         "order when possible",
+                         createSourceListDAGScheduler);
 
 namespace {
 //===----------------------------------------------------------------------===//
@@ -931,6 +936,16 @@ namespace {
     
     bool operator()(const SUnit* left, const SUnit* right) const;
   };
+
+  struct src_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
+    RegReductionPriorityQueue<src_ls_rr_sort> *SPQ;
+    src_ls_rr_sort(RegReductionPriorityQueue<src_ls_rr_sort> *spq)
+      : SPQ(spq) {}
+    src_ls_rr_sort(const src_ls_rr_sort &RHS)
+      : SPQ(RHS.SPQ) {}
+    
+    bool operator()(const SUnit* left, const SUnit* right) const;
+  };
 }  // end anonymous namespace
 
 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
@@ -981,9 +996,9 @@ namespace {
 
   public:
     RegReductionPriorityQueue(const TargetInstrInfo *tii,
-                              const TargetRegisterInfo *tri) :
-    Queue(SF(this)), currentQueueId(0),
-    TII(tii), TRI(tri), scheduleDAG(NULL) {}
+                              const TargetRegisterInfo *tri)
+      : Queue(SF(this)), currentQueueId(0),
+        TII(tii), TRI(tri), scheduleDAG(NULL) {}
     
     void initNodes(std::vector<SUnit> &sunits) {
       SUnits = &sunits;
@@ -1089,6 +1104,9 @@ namespace {
 
   typedef RegReductionPriorityQueue<td_ls_rr_sort>
     TDRegReductionPriorityQueue;
+
+  typedef RegReductionPriorityQueue<src_ls_rr_sort>
+    SrcRegReductionPriorityQueue;
 }
 
 /// closestSucc - Returns the scheduled cycle of the successor which is
@@ -1122,16 +1140,9 @@ static unsigned calcMaxScratches(const SUnit *SU) {
   return Scratches;
 }
 
-// Bottom up
-bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
-  unsigned LOrder = SPQ->getNodeOrdering(left);
-  unsigned ROrder = SPQ->getNodeOrdering(right);
-
-  // Prefer an ordering where the lower the non-zero order number, the higher
-  // the preference.
-  if ((LOrder || ROrder) && LOrder != ROrder)
-    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
-
+template <typename RRSort>
+static bool BURRSort(const SUnit *left, const SUnit *right,
+                     const RegReductionPriorityQueue<RRSort> *SPQ) {
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);
   if (LPriority != RPriority)
@@ -1176,6 +1187,24 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
   return (left->NodeQueueId > right->NodeQueueId);
 }
 
+// Bottom up
+bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
+  return BURRSort(left, right, SPQ);
+}
+
+// Source order, otherwise bottom up.
+bool src_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
+  unsigned LOrder = SPQ->getNodeOrdering(left);
+  unsigned ROrder = SPQ->getNodeOrdering(right);
+
+  // Prefer an ordering where the lower the non-zero order number, the higher
+  // the preference.
+  if ((LOrder || ROrder) && LOrder != ROrder)
+    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
+
+  return BURRSort(left, right, SPQ);
+}
+
 template<class SF>
 bool
 RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
@@ -1196,7 +1225,6 @@ RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
   return false;
 }
 
-
 /// hasCopyToRegUse - Return true if SU has a value successor that is a
 /// CopyToReg node.
 static bool hasCopyToRegUse(const SUnit *SU) {
@@ -1544,3 +1572,17 @@ llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   PQ->setScheduleDAG(SD);
   return SD;
 }
+
+llvm::ScheduleDAGSDNodes *
+llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
+  const TargetMachine &TM = IS->TM;
+  const TargetInstrInfo *TII = TM.getInstrInfo();
+  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+  
+  SrcRegReductionPriorityQueue *PQ = new SrcRegReductionPriorityQueue(TII, TRI);
+
+  ScheduleDAGRRList *SD =
+    new ScheduleDAGRRList(*IS->MF, true, PQ);
+  PQ->setScheduleDAG(SD);
+  return SD;  
+}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 67b6d5c47b..f1b6f1e831 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -593,7 +593,7 @@ void SelectionDAG::DeallocateNode(SDNode *N) {
   NodeAllocator.Deallocate(AllNodes.remove(N));
 
   // Remove the ordering of this node.
-  if (Ordering) Ordering->remove(N);
+  Ordering->remove(N);
 }
 
 /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that
@@ -790,8 +790,7 @@ SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
               getVTList(MVT::Other)),
     Root(getEntryNode()), Ordering(0) {
   AllNodes.push_back(&EntryNode);
-  if (DisableScheduling)
-    Ordering = new SDNodeOrdering();
+  Ordering = new SDNodeOrdering();
 }
 
 void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
@@ -830,8 +829,7 @@ void SelectionDAG::clear() {
   EntryNode.UseList = 0;
   AllNodes.push_back(&EntryNode);
   Root = getEntryNode();
-  if (DisableScheduling)
-    Ordering = new SDNodeOrdering();
+  Ordering = new SDNodeOrdering();
 }
 
 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) {
@@ -5241,14 +5239,13 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
 /// AssignOrdering - Assign an order to the SDNode.
 void SelectionDAG::AssignOrdering(SDNode *SD, unsigned Order) {
   assert(SD && "Trying to assign an order to a null node!");
-  if (Ordering)
-    Ordering->add(SD, Order);
+  Ordering->add(SD, Order);
 }
 
 /// GetOrdering - Get the order for the SDNode.
 unsigned SelectionDAG::GetOrdering(const SDNode *SD) const {
   assert(SD && "Trying to get the order of a null node!");
-  return Ordering ? Ordering->getOrder(SD) : 0;
+  return Ordering->getOrder(SD);
 }
 
 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index a3fb34576a..23c7059a9b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -176,7 +176,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
   assert(NumParts > 0 && "No parts to assemble!");
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue Val = Parts[0];
-  if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+  DAG.AssignOrdering(Val.getNode(), Order);
 
   if (NumParts > 1) {
     // Assemble the value from multiple parts.
@@ -209,11 +209,9 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
 
       Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
 
-      if (DisableScheduling) {
-        DAG.AssignOrdering(Lo.getNode(), Order);
-        DAG.AssignOrdering(Hi.getNode(), Order);
-        DAG.AssignOrdering(Val.getNode(), Order);
-      }
+      DAG.AssignOrdering(Lo.getNode(), Order);
+      DAG.AssignOrdering(Hi.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
 
       if (RoundParts < NumParts) {
         // Assemble the trailing non-power-of-2 part.
@@ -228,15 +226,15 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
           std::swap(Lo, Hi);
         EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
         Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
-        if (DisableScheduling) DAG.AssignOrdering(Hi.getNode(), Order);
+        DAG.AssignOrdering(Hi.getNode(), Order);
         Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
                          DAG.getConstant(Lo.getValueType().getSizeInBits(),
                                          TLI.getPointerTy()));
-        if (DisableScheduling) DAG.AssignOrdering(Hi.getNode(), Order);
+        DAG.AssignOrdering(Hi.getNode(), Order);
         Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
-        if (DisableScheduling) DAG.AssignOrdering(Lo.getNode(), Order);
+        DAG.AssignOrdering(Lo.getNode(), Order);
         Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
-        if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+        DAG.AssignOrdering(Val.getNode(), Order);
       }
     } else if (ValueVT.isVector()) {
       // Handle a multi-element vector.
@@ -277,7 +275,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       Val = DAG.getNode(IntermediateVT.isVector() ?
                         ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
                         ValueVT, &Ops[0], NumIntermediates);
-      if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
     } else if (PartVT.isFloatingPoint()) {
       // FP split into multiple FP parts (for ppcf128)
       assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
@@ -289,11 +287,9 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
         std::swap(Lo, Hi);
       Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
 
-      if (DisableScheduling) {
-        DAG.AssignOrdering(Hi.getNode(), Order);
-        DAG.AssignOrdering(Lo.getNode(), Order);
-        DAG.AssignOrdering(Val.getNode(), Order);
-      }
+      DAG.AssignOrdering(Hi.getNode(), Order);
+      DAG.AssignOrdering(Lo.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
     } else {
       // FP split into integer parts (soft fp)
       assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
@@ -312,8 +308,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
   if (PartVT.isVector()) {
     assert(ValueVT.isVector() && "Unknown vector conversion!");
     SDValue Res = DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
-    if (DisableScheduling)
-      DAG.AssignOrdering(Res.getNode(), Order);
+    DAG.AssignOrdering(Res.getNode(), Order);
     return Res;
   }
 
@@ -322,8 +317,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
            ValueVT.getVectorNumElements() == 1 &&
            "Only trivial scalar-to-vector conversions should get here!");
     SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
-    if (DisableScheduling)
-      DAG.AssignOrdering(Res.getNode(), Order);
+    DAG.AssignOrdering(Res.getNode(), Order);
     return Res;
   }
 
@@ -336,13 +330,13 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       if (AssertOp != ISD::DELETED_NODE)
         Val = DAG.getNode(AssertOp, dl, PartVT, Val,
                           DAG.getValueType(ValueVT));
-      if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
       Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
-      if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
       return Val;
     } else {
       Val = DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
-      if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
       return Val;
     }
   }
@@ -352,18 +346,18 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       // FP_ROUND's are always exact here.
       Val = DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
                         DAG.getIntPtrConstant(1));
-      if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
       return Val;
     }
 
     Val = DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
-    if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+    DAG.AssignOrdering(Val.getNode(), Order);
     return Val;
   }
 
   if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
     Val = DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
-    if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+    DAG.AssignOrdering(Val.getNode(), Order);
     return Val;
   }
 
@@ -420,7 +414,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       }
     }
 
-    if (DisableScheduling) DAG.AssignOrdering(Val.getNode(), Order);
+    DAG.AssignOrdering(Val.getNode(), Order);
 
     // The value may have changed - recompute ValueVT.
     ValueVT = Val.getValueType();
@@ -455,10 +449,8 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
       Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
 
-      if (DisableScheduling) {
-        DAG.AssignOrdering(OddVal.getNode(), Order);
-        DAG.AssignOrdering(Val.getNode(), Order);
-      }
+      DAG.AssignOrdering(OddVal.getNode(), Order);
+      DAG.AssignOrdering(Val.getNode(), Order);
     }
 
     // The number of parts is a power of 2.  Repeatedly bisect the value using
@@ -468,8 +460,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
                                              ValueVT.getSizeInBits()),
                            Val);
 
-    if (DisableScheduling)
-      DAG.AssignOrdering(Parts[0].getNode(), Order);
+    DAG.AssignOrdering(Parts[0].getNode(), Order);
 
     for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
       for (unsigned i = 0; i < NumParts; i += StepSize) {
@@ -485,20 +476,16 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
                             ThisVT, Part0,
                             DAG.getConstant(0, PtrVT));
 
-        if (DisableScheduling) {
-          DAG.AssignOrdering(Part0.getNode(), Order);
-          DAG.AssignOrdering(Part1.getNode(), Order);
-        }
+        DAG.AssignOrdering(Part0.getNode(), Order);
+        DAG.AssignOrdering(Part1.getNode(), Order);
 
         if (ThisBits == PartBits && ThisVT != PartVT) {
           Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
                                                 PartVT, Part0);
           Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
                                                 PartVT, Part1);
-          if (DisableScheduling) {
-            DAG.AssignOrdering(Part0.getNode(), Order);
-            DAG.AssignOrdering(Part1.getNode(), Order);
-          }
+          DAG.AssignOrdering(Part0.getNode(), Order);
+          DAG.AssignOrdering(Part1.getNode(), Order);
         }
       }
     }
@@ -524,9 +511,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
       }
     }
 
-    if (DisableScheduling)
-      DAG.AssignOrdering(Val.getNode(), Order);
-
+    DAG.AssignOrdering(Val.getNode(), Order);
     Parts[0] = Val;
     return;
   }
@@ -555,8 +540,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
                            IntermediateVT, Val,
                            DAG.getConstant(i, PtrVT));
 
-    if (DisableScheduling)
-      DAG.AssignOrdering(Ops[i].getNode(), Order);
+    DAG.AssignOrdering(Ops[i].getNode(), Order);
   }
 
   // Split the intermediate operands into legal parts.
@@ -717,8 +701,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
 
       SDValue Res = DAG.getMergeValues(&Constants[0], Constants.size(),
                                        getCurDebugLoc());
-      if (DisableScheduling)
-        DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
       return Res;
     }
 
@@ -744,8 +727,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
 
       SDValue Res = DAG.getMergeValues(&Constants[0], NumElts,
                                        getCurDebugLoc());
-      if (DisableScheduling)
-        DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
       return Res;
     }
 
@@ -776,9 +758,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
     // Create a BUILD_VECTOR node.
     SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
                               VT, &Ops[0], Ops.size());
-    if (DisableScheduling)
-      DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
-
+    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
     return NodeMap[V] = Res;
   }
 
@@ -895,17 +875,14 @@ void SelectionDAGBuilder::visitRet(ReturnInst &I) {
                      SDValue(RetOp.getNode(), RetOp.getResNo() + i),
                      Add, NULL, Offsets[i], false, 0);
 
-      if (DisableScheduling) {
-        DAG.AssignOrdering(Add.getNode(), SDNodeOrder);
-        DAG.AssignOrdering(Chains[i].getNode(), SDNodeOrder);
-      }
+      DAG.AssignOrdering(Add.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(Chains[i].getNode(), SDNodeOrder);
     }
 
     Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
                         MVT::Other, &Chains[0], NumValues);
 
-    if (DisableScheduling)
-      DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
+    DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
   } else {
     for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
       SmallVector<EVT, 4> ValueVTs;
@@ -971,9 +948,7 @@ void SelectionDAGBuilder::visitRet(ReturnInst &I) {
 
   // Update the DAG with the new chain value resulting from return lowering.
   DAG.setRoot(Chain);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Chain.getNode(), SDNodeOrder);
 }
 
 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
@@ -1239,9 +1214,7 @@ void SelectionDAGBuilder::visitBr(BranchInst &I) {
                               MVT::Other, getControlRoot(),
                               DAG.getBasicBlock(Succ0MBB));
       DAG.setRoot(V);
-
-      if (DisableScheduling)
-        DAG.AssignOrdering(V.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(V.getNode(), SDNodeOrder);
     }
 
     return;
@@ -1348,8 +1321,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
     }
   }
 
-  if (DisableScheduling)
-    DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
 
   // Update successor info
   CurMBB->addSuccessor(CB.TrueBB);
@@ -1368,17 +1340,13 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
     std::swap(CB.TrueBB, CB.FalseBB);
     SDValue True = DAG.getConstant(1, Cond.getValueType());
     Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
-
-    if (DisableScheduling)
-      DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
+    DAG.AssignOrdering(Cond.getNode(), SDNodeOrder);
   }
 
   SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
                                MVT::Other, getControlRoot(), Cond,
                                DAG.getBasicBlock(CB.TrueBB));
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
 
   // If the branch was constant folded, fix up the CFG.
   if (BrCond.getOpcode() == ISD::BR) {
@@ -1392,8 +1360,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
       BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
                            DAG.getBasicBlock(CB.FalseBB));
 
-      if (DisableScheduling)
-        DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
     }
   }
 
@@ -1413,11 +1380,9 @@ void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
                                     Table, Index);
   DAG.setRoot(BrJumpTable);
 
-  if (DisableScheduling) {
-    DAG.AssignOrdering(Index.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(Table.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(BrJumpTable.getNode(), SDNodeOrder);
-  }
+  DAG.AssignOrdering(Index.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Table.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(BrJumpTable.getNode(), SDNodeOrder);
 }
 
 /// visitJumpTableHeader - This function emits necessary code to produce index
@@ -1452,12 +1417,10 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
                              DAG.getConstant(JTH.Last-JTH.First,VT),
                              ISD::SETUGT);
 
-  if (DisableScheduling) {
-    DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(SwitchOp.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(CMP.getNode(), SDNodeOrder);
-  }
+  DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(SwitchOp.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(CMP.getNode(), SDNodeOrder);
 
   // Set NextBlock to be the MBB immediately after the current one, if any.
   // This is used to avoid emitting unnecessary branches to the next block.
@@ -1471,15 +1434,12 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
                                MVT::Other, CopyTo, CMP,
                                DAG.getBasicBlock(JT.Default));
 
-  if (DisableScheduling)
-    DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
 
   if (JT.MBB != NextBlock) {
     BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
                          DAG.getBasicBlock(JT.MBB));
-
-    if (DisableScheduling)
-      DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
+    DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
   }
 
   DAG.setRoot(BrCond);
@@ -1507,12 +1467,10 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
                                     B.Reg, ShiftOp);
 
-  if (DisableScheduling) {
-    DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(RangeCmp.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
-  }
+  DAG.AssignOrdering(Sub.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(RangeCmp.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(CopyTo.getNode(), SDNodeOrder);
 
   // Set NextBlock to be the MBB immediately after the current one, if any.
   // This is used to avoid emitting unnecessary branches to the next block.
@@ -1530,15 +1488,12 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
                                 MVT::Other, CopyTo, RangeCmp,
                                 DAG.getBasicBlock(B.Default));
 
-  if (DisableScheduling)
-    DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
 
   if (MBB != NextBlock) {
     BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
                           DAG.getBasicBlock(MBB));
-
-    if (DisableScheduling)
-      DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
+    DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
   }
 
   DAG.setRoot(BrRange);
@@ -1565,12 +1520,10 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
                                 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
                                 ISD::SETNE);
 
-  if (DisableScheduling) {
-    DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(SwitchVal.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(AndOp.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(AndCmp.getNode(), SDNodeOrder);
-  }
+  DAG.AssignOrdering(ShiftOp.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(SwitchVal.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(AndOp.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(AndCmp.getNode(), SDNodeOrder);
 
   CurMBB->addSuccessor(B.TargetBB);
   CurMBB->addSuccessor(NextMBB);
@@ -1579,8 +1532,7 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
                               MVT::Other, getControlRoot(),
                               AndCmp, DAG.getBasicBlock(B.TargetBB));
 
-  if (DisableScheduling)
-    DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
 
   // Set NextBlock to be the MBB immediately after the current one, if any.
   // This is used to avoid emitting unnecessary branches to the next block.
@@ -1592,9 +1544,7 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
   if (NextMBB != NextBlock) {
     BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
                         DAG.getBasicBlock(NextMBB));
-
-    if (DisableScheduling)
-      DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
+    DAG.AssignOrdering(BrAnd.getNode(), SDNodeOrder);
   }
 
   DAG.setRoot(BrAnd);
@@ -1624,9 +1574,7 @@ void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
                                MVT::Other, getControlRoot(),
                                DAG.getBasicBlock(Return));
   DAG.setRoot(Branch);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Branch.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Branch.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
@@ -2143,9 +2091,7 @@ void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
                                 MVT::Other, getControlRoot(),
                                 DAG.getBasicBlock(Default));
       DAG.setRoot(Res);
-
-      if (DisableScheduling)
-        DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+      DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
     }
 
     return;
@@ -2203,9 +2149,7 @@ void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
                             MVT::Other, getControlRoot(),
                             getValue(I.getAddress()));
   DAG.setRoot(Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFSub(User &I) {
@@ -2223,10 +2167,7 @@ void SelectionDAGBuilder::visitFSub(User &I) {
         SDValue Res = DAG.getNode(ISD::FNEG, getCurDebugLoc(),
                                   Op2.getValueType(), Op2);
         setValue(&I, Res);
-
-        if (DisableScheduling)
-          DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
-
+        DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
         return;
       }
     }
@@ -2238,10 +2179,7 @@ void SelectionDAGBuilder::visitFSub(User &I) {
       SDValue Res = DAG.getNode(ISD::FNEG, getCurDebugLoc(),
                                 Op2.getValueType(), Op2);
       setValue(&I, Res);
-
-      if (DisableScheduling)
-        DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
-
+      DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
       return;
     }
 
@@ -2254,9 +2192,7 @@ void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
   SDValue Res = DAG.getNode(OpCode, getCurDebugLoc(),
                             Op1.getValueType(), Op1, Op2);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
@@ -2292,12 +2228,9 @@ void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
   SDValue Res = DAG.getNode(Opcode, getCurDebugLoc(),
                             Op1.getValueType(), Op1, Op2);
   setValue(&I, Res);
-
-  if (DisableScheduling) {
-    DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(Op2.getNode(), SDNodeOrder);
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
-  }
+  DAG.AssignOrdering(Op1.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Op2.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitICmp(User &I) {
@@ -2313,9 +2246,7 @@ void SelectionDAGBuilder::visitICmp(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFCmp(User &I) {
@@ -2330,9 +2261,7 @@ void SelectionDAGBuilder::visitFCmp(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitSelect(User &I) {
@@ -2354,17 +2283,14 @@ void SelectionDAGBuilder::visitSelect(User &I) {
                             SDValue(FalseVal.getNode(),
                                     FalseVal.getResNo() + i));
 
-    if (DisableScheduling)
-      DAG.AssignOrdering(Values[i].getNode(), SDNodeOrder);
+    DAG.AssignOrdering(Values[i].getNode(), SDNodeOrder);
   }
 
   SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
                             DAG.getVTList(&ValueVTs[0], NumValues),
                             &Values[0], NumValues);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitTrunc(User &I) {
@@ -2373,9 +2299,7 @@ void SelectionDAGBuilder::visitTrunc(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitZExt(User &I) {
@@ -2385,9 +2309,7 @@ void SelectionDAGBuilder::visitZExt(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitSExt(User &I) {
@@ -2397,9 +2319,7 @@ void SelectionDAGBuilder::visitSExt(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFPTrunc(User &I) {
@@ -2409,9 +2329,7 @@ void SelectionDAGBuilder::visitFPTrunc(User &I) {
   SDValue Res = DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
                             DestVT, N, DAG.getIntPtrConstant(0));
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFPExt(User &I){
@@ -2420,9 +2338,7 @@ void SelectionDAGBuilder::visitFPExt(User &I){
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFPToUI(User &I) {
@@ -2431,9 +2347,7 @@ void SelectionDAGBuilder::visitFPToUI(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitFPToSI(User &I) {
@@ -2442,9 +2356,7 @@ void SelectionDAGBuilder::visitFPToSI(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitUIToFP(User &I) {
@@ -2453,9 +2365,7 @@ void SelectionDAGBuilder::visitUIToFP(User &I) {
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)
-    DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
+  DAG.AssignOrdering(Res.getNode(), SDNodeOrder);
 }
 
 void SelectionDAGBuilder::visitSIToFP(User &I){
@@ -2464,9 +2374,7 @@ void SelectionDAGBuilder::visitSIToFP(User &I){
   EVT DestVT = TLI.getValueType(I.getType());
   SDValue Res = DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N);
   setValue(&I, Res);
-
-  if (DisableScheduling)