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| author | Evan Cheng <evan.cheng@apple.com> | 2007-12-06 22:14:22 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-12-06 22:14:22 +0000 |
| commit | 1076210ee30c7b0ed2b43830d0aa7bd3c3218547 (patch) | |
| tree | 5dcc7a0166ecb747cbff04861473a0f0fb11a4d0 | |
| parent | b0e370abdfb593fce9a4beb570c716e2234ad703 (diff) | |
Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44669 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 6 |
2 files changed, 1 insertions, 7 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 505c302816..15286cce7e 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2462,7 +2462,7 @@ bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { /// specifies a shuffle of elements that is suitable for input to MOVSS, /// MOVSD, and MOVD, i.e. setting the lowest element. static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) { - if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) + if (NumElts != 2 && NumElts != 4) return false; if (!isUndefOrEqual(Elts[0], NumElts)) diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index da23ccbaa0..a196dce1b8 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2734,12 +2734,6 @@ let Predicates = [HasSSE2] in { // Move scalar to XMM zero-extended // movd to XMM register zero-extends let AddedComplexity = 15 in { -def : Pat<(v8i16 (vector_shuffle immAllZerosV_bc, - (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)), - (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>; -def : Pat<(v16i8 (vector_shuffle immAllZerosV_bc, - (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)), - (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>; // Zeroing a VR128 then do a MOVS{S|D} to the lower bits. def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)), |