diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-27 00:33:08 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-27 00:33:08 +0000 |
| commit | 08b93c6a70ae59af375f205cfcffeaa3517577ab (patch) | |
| tree | 6a22550dc1634f7b7d287a25900e79950f0e62de | |
| parent | dced03fc846fa7cd9558ecb8e33ca98ec29bdcf0 (diff) | |
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 15 |
2 files changed, 12 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 93ac1d53d8..059f2bfe4e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -612,7 +612,7 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } if (DestRC == ARM::GPRRegisterClass) - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg).addReg(SrcReg))); else if (DestRC == ARM::SPRRegisterClass) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index d74e485d08..421f7f9807 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -84,14 +84,21 @@ Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, DebugLoc DL = DebugLoc::getUnknownLoc(); if (I != MBB.end()) DL = I->getDebugLoc(); - if ((DestRC == ARM::GPRRegisterClass && - SrcRC == ARM::tGPRRegisterClass) || - (DestRC == ARM::tGPRRegisterClass && - SrcRC == ARM::GPRRegisterClass)) { + if (DestRC == ARM::GPRRegisterClass && + SrcRC == ARM::GPRRegisterClass) { AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2MOVr), DestReg).addReg(SrcReg))); return true; + } else if (DestRC == ARM::GPRRegisterClass && + SrcRC == ARM::tGPRRegisterClass) { + BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg); + return true; + } else if (DestRC == ARM::tGPRRegisterClass && + SrcRC == ARM::GPRRegisterClass) { + BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); + return true; } + // Handle SPR, DPR, and QPR copies. return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC); } |