emscripten-fastcomp/utils/TableGen/CodeGenRegisters.h, branch 1.17.0LLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/utils/TableGen/CodeGenRegisters.h?h=1.17.02013-03-17T17:26:09ZUse ArrayRef<MVT::SimpleValueType> when possible.2013-03-17T17:26:09ZJakob Stoklund Olesenstoklund@2pi.dk2013-03-17T17:26:09Zurn:sha1:26369a930c523b75fe8f4ba18456ff86f68d5612
Not passing vector references around makes it possible to use
SmallVector in most places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
RegisterPressure API. Add support for physical register units.2012-12-05T06:47:12ZAndrew Trickatrick@apple.com2012-12-05T06:47:12Zurn:sha1:eca1fcf3d2d8246c45648fea59bd21a4091f9115
At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).
Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
Sort the #include lines for utils/...2012-12-04T10:37:14ZChandler Carruthchandlerc@gmail.com2012-12-04T10:37:14Zurn:sha1:4ffd89fa4d2788611187d1a534d2ed46adf1702c
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 1647672012-09-27T10:14:43ZSylvestre Ledrusylvestre@debian.org2012-09-27T10:14:43Zurn:sha1:94c22716d60ff5edf6a98a3c67e0faa001be1142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a typo 'iff' => 'if'2012-09-27T09:59:43ZSylvestre Ledrusylvestre@debian.org2012-09-27T09:59:43Zurn:sha1:7e2c793a2b5c746344652b6579e958ee42fafdcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.2012-09-11T23:32:17ZOwen Andersonresistor@mac.com2012-09-11T23:32:17Zurn:sha1:d2c699706ceae4a118a8dcafbef73b85093e5390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
Add TRI::getSubRegIndexLaneMask().2012-09-11T16:34:08ZJakob Stoklund Olesenstoklund@2pi.dk2012-09-11T16:34:08Zurn:sha1:a6035773d8d29827a124e65c258adbf0dcbb1a5a
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.
The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.
Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
Clean the sub-reg index composition maps at emission.2012-09-11T16:34:05ZJakob Stoklund Olesenstoklund@2pi.dk2012-09-11T16:34:05Zurn:sha1:de0250728b1a9e69ca593168f1ea2ecef8e9bf95
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
Make synthesized sub-register indexes available in the target namespace.2012-08-15T18:00:55ZJakob Stoklund Olesenstoklund@2pi.dk2012-08-15T18:00:55Zurn:sha1:c97eda2c9e34f4c491f59bbac81af2fd63fef49d
TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.
Also take this opportunity to stop creating new Record objects for
synthetic indexes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
Remove little semicolon that caused a lot of warnings.2012-05-30T09:13:49ZBenjamin Kramerbenny.kra@googlemail.com2012-05-30T09:13:49Zurn:sha1:dee3be60292ecfafe584baf4ed84b634b8f4c7c7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8