emscripten-fastcomp/tools/opt, branch master

NoExitRuntime

2014-02-26T17:37:10Z

boilerplate for ExpandI64Pass

2013-12-04T18:57:52Z

Add PNaClSjLjEH pass to implement C++ exception handling using setjmp()+longjmp()

2013-10-16T20:06:24Z

There are two parts to this: * PNaClSjLjEH.cpp expands out the "invoke", "landingpad" and "resume" instructions, modifying the control flow to use setjmp(). * ExceptionInfoWriter.cpp lowers landingpads' clause lists to data that PNaCl's C++ runtime library will interpret. This part will be reused when we drop the SjLj part and create a stable ABI for zero-cost EH. This pass isn't enabled in PNaClABISimplify yet: I'll do that in a separate change. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3696 TEST=*.ll tests (also tested end-to-end: plumbing for this will follow later) Review URL: https://codereview.chromium.org/24777002

Use ARM TTI in "opt" to make up for missing LE32 TTI.

2013-09-16T20:33:23Z

Since we deleted the rewrite of ARM -> LE32 in the bitcode reader, opt is unable to look up a TTI to transform switch(c) { case 1: x = ; break; case 2: x = ; break; ... } into a lookup table to get x from c. This causes a regression in pnacl-llc's size (which has lots of switch statements). Fake the target lookup in opt for now. Eventually we should look into making target info for le32. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2554 TEST= trybot http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/887 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/842 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/23551013

Add the new @llvm.nacl.atomic.fence.all intrinsic

2013-08-07T22:50:54Z

This is a follow-up to: https://codereview.chromium.org/22240002/ And requires the Clang changes from: https://codereview.chromium.org/22294002/ This new intrinsic represents ``asm("":::"~{memory}")`` as well as ``__sync_synchronize()``, and in IR it corresponds to a sequentially-consistent fence surrounded by ``call void asm sideeffect "", "~{memory}"()``. R=jvoung@chromium.org TEST= ninja check-all BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 Review URL: https://codereview.chromium.org/22474008

Rewrite ``asm("":::"memory")`` to ``fence seq_cst``

2013-07-30T23:38:26Z

This is often used as a compiler barrier and should "just work" in user code. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2345 R=eliben@chromium.org TEST= (cd ./pnacl/build/llvm_x86_64 && ninja check-all) Review URL: https://codereview.chromium.org/21178002

Merge remote-tracking branch 'origin/master'

2013-07-19T01:00:27Z

Make it compile

2013-07-16T17:52:19Z

Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'

2013-07-15T23:09:15Z

Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp

Concurrency support for PNaCl ABI

2013-07-13T20:29:35Z

Add portable support for concurrency in PNaCl's ABI: - Promote volatile to atomic. - Promote all memory ordering to sequential consistency. - Rewrite all atomic operations to frozen NaCl intrinsics for pexe. - Rewrite atomic intrinsics to LLVM instructions for translation. This change also adds documentation to the PNaCl language reference, as well as tests where it makes sense. A future CL could clean up more of our code which mentions atomics, volatiles, memory orderings. Multiple reviewers because this is a big patch: - eliben: LLVM-fu and ResolvePNaClIntrinsics. - dschuff: ABI stability. - mseaborn: ABI stability. - sehr: Tron-duty (fight for the user's programs to work). BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 R=dschuff@chromium.org, eliben@chromium.org, sehr@google.com TEST= (cd ./pnacl/build/llvm_x86_64; ninja check-all) && ./pnacl/test.sh test-x86-32 && ./pnacl/test.sh test-x86-64 && ./pnacl/test.sh test-arm && ./pnacl/test.sh test-x86-32-sbtc && ./pnacl/test.sh test-x86-64-sbtc && ./pnacl/test.sh test-arm-sbtc Review URL: https://codereview.chromium.org/17777004