LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/test/MC?h=master 2013-07-16T21:34:27Z 2013-07-16T21:34:27Z Eli Bendersky eliben@chromium.org 2013-07-16T21:34:27Z urn:sha1:af56c404f86351c203c5c14181c42553dc2215e3 2013-07-15T23:09:15Z Eli Bendersky eliben@chromium.org 2013-07-15T23:09:15Z urn:sha1:c6cf05cb5108f356dde97c01ee4188b0671d4542 Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp 2013-05-29T23:47:25Z JF Bastien jfb@chromium.org 2013-05-29T23:47:25Z urn:sha1:69671d8bdefb36d637a20efae3f3e5cec297fb40 ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15737029 2013-05-21T23:47:17Z Bill Wendling isanbard@gmail.com 2013-05-21T23:47:17Z urn:sha1:595bc150b4c13f739c9bd587290d6406f2f177b4 ------------------------------------------------------------------------ r181366 | enderby | 2013-05-07 14:40:58 -0700 (Tue, 07 May 2013) | 6 lines Fix a bug in the MC asm parser evaluating expressions. It was treating: A = 9 B = 3 * A - 2 * A + 1 as B = 3 * A - (2 * A + 1) rdar://13816516 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182438 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-10T23:00:11Z Derek Schuff dschuff@chromium.org 2013-05-10T23:00:11Z urn:sha1:52daf9d821c963f84dd312ff90921bfe1b1cc0a1 This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009 2013-05-06T16:20:58Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-06T16:20:58Z urn:sha1:097b88fff6c091e3ce314d1b5fe89ed3e691b261 This adds all MC tests for the SystemZ target. Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181206 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-05T13:36:53Z Richard Osborne richard@xmos.com 2013-05-05T13:36:53Z urn:sha1:589ddc9887406ddfd5a2661b567057faad7a22cc With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-05T13:24:16Z Richard Osborne richard@xmos.com 2013-05-05T13:24:16Z urn:sha1:c601bd69d5c7fcd3bf9946e8a8a1bd1f9ab6642b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:52:35Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:52:35Z urn:sha1:a7e5e6b959bfd2b7982e116a4fd6955b35534b4c This patch adds support for PowerPC platform-specific variant kinds in MCSymbolRefExpr::getVariantKindForName, and also adds a test case to verify they are translated to the appropriate fixup type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:51:09Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:51:09Z urn:sha1:8e4ba8f7b19615907e5874b3aa661d52c21fff74 This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8