emscripten-fastcomp/test/MC/Disassembler/XCore, branch master LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/test/MC/Disassembler/XCore?h=master 2013-05-05T13:36:53Z [XCore] Add LDAPB instructions. 2013-05-05T13:36:53Z Richard Osborne richard@xmos.com 2013-05-05T13:36:53Z urn:sha1:589ddc9887406ddfd5a2661b567057faad7a22cc With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add BLRB instructions. 2013-05-05T13:24:16Z Richard Osborne richard@xmos.com 2013-05-05T13:24:16Z urn:sha1:c601bd69d5c7fcd3bf9946e8a8a1bd1f9ab6642b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8 Use object file specific section type for initial text section 2013-04-14T21:18:36Z Nico Rieck nico.rieck@gmail.com 2013-04-14T21:18:36Z urn:sha1:ef1762b6a1d3353790bdb415788e7d8963e70372 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add bru instruction. 2013-04-04T20:05:35Z Richard Osborne richard@xmos.com 2013-04-04T20:05:35Z urn:sha1:e50faa754b946d5240c1d4e84e64b7e84d4e27b1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] The RRegs register class is a superset of GRRegs. 2013-04-04T19:57:46Z Richard Osborne richard@xmos.com 2013-04-04T19:57:46Z urn:sha1:c6ff29713d69b4a41c225cbde9c82e4a350dbfac At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Check disassembly of the st8 instruction. 2013-04-03T20:07:11Z Richard Osborne richard@xmos.com 2013-04-03T20:07:11Z urn:sha1:6107bbbbdf1c801b80f28a4d20e2194087f13c62 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Update disassembler test to improve coverage of the instructions. 2013-04-03T20:07:06Z Richard Osborne richard@xmos.com 2013-04-03T20:07:06Z urn:sha1:ef6343347a9269f17c1c723d6afaa28a5e5a5714 Previously some instructions were unintentionally covered twice and others were not covered at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing 2r instructions. 2013-02-17T22:38:05Z Richard Osborne richard@xmos.com 2013-02-17T22:38:05Z urn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add TSETR instruction. 2013-02-17T22:32:41Z Richard Osborne richard@xmos.com 2013-02-17T22:32:41Z urn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing u10 / lu10 instructions. 2013-02-17T20:44:48Z Richard Osborne richard@xmos.com 2013-02-17T20:44:48Z urn:sha1:a970dde9060d8994c242bd186bb3636d2caf22d2 These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8