emscripten-fastcomp/test/MC/Disassembler/Mips, branch master LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/test/MC/Disassembler/Mips?h=master 2013-04-18T00:52:44Z [mips] DSP-ASE move from HI/LO register instructions. 2013-04-18T00:52:44Z Akira Hatanaka ahatanaka@mips.com 2013-04-18T00:52:44Z urn:sha1:26aef5b7d64e2dd2ed49123baf1e1075b648824f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8 Use object file specific section type for initial text section 2013-04-14T21:18:36Z Nico Rieck nico.rieck@gmail.com 2013-04-14T21:18:36Z urn:sha1:ef1762b6a1d3353790bdb415788e7d8963e70372 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8 This is a resubmittal. For some reason it broke the bots yesterday 2013-01-17T00:28:20Z Jack Carter jcarter@mips.com 2013-01-17T00:28:20Z urn:sha1:c147b678206db510336ee95c3b55dc9c0ff19595 but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8 reverting 172579 2013-01-16T01:29:10Z Jack Carter jcarter@mips.com 2013-01-16T01:29:10Z urn:sha1:457ee1a12e2c52624af7fdb81cf938f6d8d96572 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8 Akira, 2013-01-16T00:07:45Z Jack Carter jcarter@mips.com 2013-01-16T00:07:45Z urn:sha1:490c7d97737ea7719efcea7321d3cfa3984b0027 Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8 Remove DOS line endings. 2012-11-14T20:18:34Z Jakub Staszak kubastaszak@gmail.com 2012-11-14T20:18:34Z urn:sha1:de7c8530c85181c78fbb30a305749ee3a71cfc51 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Fix disassembler test cases. 2012-11-02T22:20:10Z Akira Hatanaka ahatanaka@mips.com 2012-11-02T22:20:10Z urn:sha1:53e93e85e00693d904861532350383ceaf330bca git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8 Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck. 2012-07-12T21:19:32Z Akira Hatanaka ahatanaka@mips.com 2012-07-12T21:19:32Z urn:sha1:94e36e34e260822bf3249f0a48f400f3d28a4e58 Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8 Reapply r158846. 2012-07-09T18:46:47Z Akira Hatanaka ahatanaka@mips.com 2012-07-09T18:46:47Z urn:sha1:241b77fa451f8076e47c37212028454ad52ece15 Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8 revert r159851. 2012-07-06T20:16:48Z Akira Hatanaka ahatanaka@mips.com 2012-07-06T20:16:48Z urn:sha1:63d10fbc89c02758cd91e3b53749e55c2bd0cf65 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8