emscripten-fastcomp/test/CodeGen/X86/vec_compare.ll, branch 1.13.2 LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/test/CodeGen/X86/vec_compare.ll?h=1.13.2 2013-05-22T17:23:54Z Merging r182486: 2013-05-22T17:23:54Z Bill Wendling isanbard@gmail.com 2013-05-22T17:23:54Z urn:sha1:62131ab28074e0ef5545775c248c2905d09e498c ------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8 Merging r182364: 2013-05-21T20:13:22Z Bill Wendling isanbard@gmail.com 2013-05-21T20:13:22Z urn:sha1:5f5295224d58e17265177bac127563e605bf5cab ------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8 X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't available. 2013-04-18T21:37:45Z Benjamin Kramer benny.kra@googlemail.com 2013-04-18T21:37:45Z urn:sha1:fcba22decb8f44ff9aa8807f275ca3a32589fba0 This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. 2012-12-25T13:09:08Z Benjamin Kramer benny.kra@googlemail.com 2012-12-25T13:09:08Z urn:sha1:99f78061e05833e815cb7a27e6c17eadcd028ce2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8 X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. 2012-12-25T12:54:19Z Benjamin Kramer benny.kra@googlemail.com 2012-12-25T12:54:19Z urn:sha1:382ed78d3fef9f6c582e3cdcfb30f8c6fa3d0d79 pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack. Small speedup on loop-vectorized viterbi (-march=core2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8 X86 Peephole: fold loads to the source register operand if possible. 2012-08-02T19:37:32Z Manman Ren mren@apple.com 2012-08-02T19:37:32Z urn:sha1:127eea87d666ccc9fe7025f41148c33af0f8c84b Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8 X86 Peephole: fold loads to the source register operand if possible. 2012-08-02T00:56:42Z Manman Ren mren@apple.com 2012-08-02T00:56:42Z urn:sha1:d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2d Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8 Revert r160920 and r160919 due to dragonegg and clang selfhost failure 2012-07-29T02:44:09Z Manman Ren mren@apple.com 2012-07-29T02:44:09Z urn:sha1:e8b4a4a9d173d67e35e4b1d32e20140381db6bde git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8 X86 Peephole: fold loads to the source register operand if possible. 2012-07-28T17:51:24Z Manman Ren mren@apple.com 2012-07-28T17:51:24Z urn:sha1:14148c41d999390517cfc4ca36d866ae2c044500 Trying to fix the bot by specifying a triple in the failing testing cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160920 91177308-0d34-0410-b5e6-96231b3b80d8 X86 Peephole: fold loads to the source register operand if possible. 2012-07-28T16:48:01Z Manman Ren mren@apple.com 2012-07-28T16:48:01Z urn:sha1:0eb3edea9cb6819334173a7d288da85943201fe5 Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8