emscripten-fastcomp/test/CodeGen/X86/fast-isel-bc.ll, branch 1.13.2

RegAlloc superpass: includes phi elimination, coalescing, and scheduling.

2012-02-10T04:10:36Z

Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate more linear scan tests.

2011-11-12T20:35:26Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144462 91177308-0d34-0410-b5e6-96231b3b80d8

Mark all these as needing SSE2. Should fix PPC and

2010-10-01T04:17:55Z

maybe even Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115291 91177308-0d34-0410-b5e6-96231b3b80d8

Massive rewrite of MMX:

2010-09-30T23:57:10Z

The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8

Add a -regalloc=default option that chooses a register allocator based on the -O

2010-05-27T23:57:25Z

optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate more uses of llvm-as and llvm-dis.

2009-09-08T23:54:48Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8

Teach X86FastISel how to handle CCValAssign::BCvt, which is used for

2009-08-05T05:33:42Z

MMX arguments. This fixes PR4684. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8