emscripten-fastcomp/test/CodeGen/Mips, branch master

Apply upstream: [mips] Fix a bug in MipsLongBranch::replaceBranch

2013-10-11T01:35:47Z

Cherry-pick r191978 from upstream. Original commit message: Author: Akira Hatanaka Date: Fri Oct 4 20:51:40 2013 +0000 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing instructions in delay slots along with the original branch instructions This has to be cherrypicked, as it is a bug in backend. It was exposed in a long function inside of llc, which caused llc.nexe to work incorrectly. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= bug in MIPS backend Review URL: https://codereview.chromium.org/26933005

Apply upstream: [mips] Implement llvm.trap intrinsic.

2013-10-11T01:30:21Z

Cherry-pick r187244 from upstream. Original commit message: Author: Akira Hatanaka Date: Fri Jul 26 20:58:55 2013 +0000 [mips] Implement llvm.trap intrinsic. Patch by Sasa Stankovic. This has to be cherrypicked, as two tests fail due to missing llvm.trap intrinsic. The tests are: - run_sysbrk_test - run_abi_types_test TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= sysbrk and abi_types tests fail for MIPS Review URL: https://codereview.chromium.org/26953003

Apply upstream: [mips] Trap on integer division by zero.

2013-10-11T00:58:15Z

Cherry-pick r182306 from upstream. Original commit message: Author: Akira Hatanaka Date: Mon May 20 18:07:43 2013 +0000 [mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= missing trap for MIPS Review URL: https://codereview.chromium.org/26846007

Remove some uneeded pseudos in the presence of the naked function attribute.

2013-05-03T23:17:24Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Split the DSP control register and define one register for each field of

2013-05-03T18:37:49Z

its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Handle reading, writing or copying of ccond field of DSP control

2013-05-02T23:07:05Z

register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Fix handling of instructions which copy to/from accumulator registers.

2013-04-30T23:22:09Z

Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Instruction selection patterns for DSP-ASE vector select and compare

2013-04-30T22:37:26Z

instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8

TBAA: remove !tbaa from testing cases if not used.

2013-04-30T17:52:57Z

This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] In performDSPShiftCombine, check that all elements in the vector are

2013-04-22T19:58:23Z

shifted by the same amount and the shift amount is smaller than the element size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8