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<title>emscripten-fastcomp/test/CodeGen/Hexagon, branch master</title>
<subtitle>LLVM with the emscripten fastcomp javascript backend</subtitle>
<id>https://git.amat.us/emscripten-fastcomp/atom/test/CodeGen/Hexagon?h=master</id>
<link rel='self' href='https://git.amat.us/emscripten-fastcomp/atom/test/CodeGen/Hexagon?h=master'/>
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<updated>2013-10-11T22:27:57Z</updated>
<entry>
<title>Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.</title>
<updated>2013-10-11T22:27:57Z</updated>
<author>
<name>Jan Voung</name>
<email>jvoung@chromium.org</email>
</author>
<published>2013-10-11T22:27:57Z</published>
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<id>urn:sha1:c036ceaa8225a23a795b50144b1da4b883e984a3</id>
<content type='text'>
See:
http://llvm.org/viewvc/llvm-project?view=revision&amp;revision=187787

The newer version of newlib tickles this x86-32 bug
when building the exception handling tests, which don't
strip the "tail" attribute.

BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702

Waiting on trybots, but it seems to have fixed the minimal
reproducer I have:
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875

R=jfb@chromium.org

Review URL: https://codereview.chromium.org/26538008
</content>
</entry>
<entry>
<title>Hexagon - Add peephole optimizations for zero extends.</title>
<updated>2013-05-02T20:22:51Z</updated>
<author>
<name>Pranav Bhandarkar</name>
<email>pranavb@codeaurora.org</email>
</author>
<published>2013-05-02T20:22:51Z</published>
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<id>urn:sha1:02d937d86420409210291accd9aa023d97b4a8b5</id>
<content type='text'>
	* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32-&gt;i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>TBAA: remove !tbaa from testing cases if not used.</title>
<updated>2013-04-30T17:52:57Z</updated>
<author>
<name>Manman Ren</name>
<email>mren@apple.com</email>
</author>
<published>2013-04-30T17:52:57Z</published>
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<id>urn:sha1:2dc50d306752c8672d1543feb88517705cdb25e7</id>
<content type='text'>
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.</title>
<updated>2013-04-23T21:17:40Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-04-23T21:17:40Z</published>
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<id>urn:sha1:42ba77db537274c797d74ddfa80902e58901529a</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Remove assembler mapped instruction definitions.</title>
<updated>2013-04-23T19:15:55Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-04-23T19:15:55Z</published>
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<id>urn:sha1:47089c91aea7bdd8b2fa81223dfdd3484a20fd12</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Remove duplicate instructions to handle global/immediate values</title>
<updated>2013-04-23T17:11:46Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-04-23T17:11:46Z</published>
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<id>urn:sha1:3d7b39e7d4d3cef9f859f5965fbf959e251ee3ee</id>
<content type='text'>
for absolute/absolute-set addressing modes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.</title>
<updated>2013-03-28T19:34:49Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-03-28T19:34:49Z</published>
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<id>urn:sha1:e41c7d4890c8363f21bee4a2a9414760ff24e473</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Use multiclass for gp-relative instructions.</title>
<updated>2013-03-28T16:25:57Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-03-28T16:25:57Z</published>
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<id>urn:sha1:4f2ef94d6ad77cbdef068e85674d0101d331051e</id>
<content type='text'>
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.</title>
<updated>2013-03-26T15:43:57Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-03-26T15:43:57Z</published>
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<id>urn:sha1:7bb9585c6e2528e3e4e928e7691dd97a106e3de0</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Hexagon: Add and enable memops setbit, clrbit, &amp;,|,+,- for byte, short, and word.</title>
<updated>2013-03-22T18:41:34Z</updated>
<author>
<name>Jyotsna Verma</name>
<email>jverma@codeaurora.org</email>
</author>
<published>2013-03-22T18:41:34Z</published>
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<id>urn:sha1:97e602b574b38d57384f0f877700357531a3d23e</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
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