emscripten-fastcomp/test/CodeGen/ARM, branch master

Apply upstream: Add missing ATOMIC_CMP_SWAP case.

2013-10-11T01:20:45Z

Cherry-pick r185186 from upstream. Original commit message: Author: Lang Hames Date: Fri Jun 28 18:36:42 2013 +0000 Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP. Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash during isel. This has to be cherry-picked, as we have experienced the same bug described in the original message. Missing case caused MIPS 64 atomics to crash. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= crash for MIPS atomics Review URL: https://codereview.chromium.org/26958002

Cherrypick test from r186226 - Fix ARM paired GPR COPY lowering

2013-07-23T16:06:31Z

BUG= test the fix that was already cherrypicked TEST= self R=eliben@chromium.org Review URL: https://codereview.chromium.org/19704008

Cherrypick upstream ARM FastISel ext patches

2013-07-22T21:02:50Z

Specifically: r186489 - Fix ARMFastISel::ARMEmitIntExt shift emission r183794 - ARM FastISel fix sext/zext fold r183601 - Fix unused variable warning from my previous patch r183551 - ARM FastISel integer sext/zext improvements These should fix some failures that I had run into back then, as well as make ARM FastISel faster because it doesn't go to SelectionDAG. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jvoung@chromium.org TEST= make check-all Review URL: https://codereview.chromium.org/19992002

Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'

2013-07-15T23:09:15Z

Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp

Revert "Apply upstream r183551, r183601, r183624 and r183794"

2013-06-25T20:53:13Z

Revert this until we fix i1 sext. Currently, it uses LSL and ASR, which are pseudo-instructions and get dropped on the floor when generating .o files. We'll fix that, but for now revert to green the bots. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jfb@chromium.org Review URL: https://codereview.chromium.org/17715002

Fix PrologEpilogInserter to save and restore all callee saved registers

2013-06-13T23:04:07Z

if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002

Apply upstream r183551, r183601, r183624 and r183794

2013-06-11T22:49:41Z

Rename countTrailingZeros to the older CountTrailingZeros_32, mark as localmod. These patches fix correctness issues with ARM FastISel, and should make it faster while generating better code. BUG= none TEST= self R=jvoung@chromium.org Review URL: https://codereview.chromium.org/16712002

Apply LLVM upstream: r182877 - Enable FastISel on ARM for Linux and NaCl

2013-05-31T21:46:24Z

This also pulls in a TargetMachine.h change from r176986 and changes NaCl's intrinsics-bitmanip.ll test to account for register spills at O0. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. R=dschuff@chromium.org, jvoung@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=3120 Review URL: https://codereview.chromium.org/15671004

Apply LLVM upstream: r181801 - Fix ARM FastISel tests, as a first step to enabling ARM FastISel

2013-05-29T23:47:25Z

ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15737029

Apply LLVM upstream: r182175 - Support unaligned load/store on more ARM targets

2013-05-29T23:45:58Z

This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15677005