emscripten-fastcomp/lib/Target/XCore/Makefile, branch masterLLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/XCore/Makefile?h=master2012-12-16T17:37:34ZAdd instruction encodings and disassembly for 1r instructions.2012-12-16T17:37:34ZRichard Osbornerichard@xmos.com2012-12-16T17:37:34Zurn:sha1:54d6266e9baa8c2796c4a95c35897b5c67d8d910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
Add XCore disassembler.2012-12-16T17:29:14ZRichard Osbornerichard@xmos.com2012-12-16T17:29:14Zurn:sha1:881e3cca66c64a57ff431a4f6d1136dd6017c137
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.2012-12-16T16:20:48ZRichard Osbornerichard@xmos.com2012-12-16T16:20:48Zurn:sha1:9578d793c9450b315721d5cb15001c2e69bff3d0
This change adds XCoreMCInstLower to do the lowering to MCInst and
XCoreInstPrinter to print the MCInsts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170288 91177308-0d34-0410-b5e6-96231b3b80d8
Next round of MC refactoring. This patch factor MC table instantiations, MC2011-07-14T20:59:42ZEvan Chengevan.cheng@apple.com2011-07-14T20:59:42Zurn:sha1:c60f9b752381baa6c4b80c0739034660f1748c84
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.2011-07-01T22:36:09ZEvan Chengevan.cheng@apple.com2011-07-01T22:36:09Zurn:sha1:385e930d55f3ecd3c9538823dfa5896a12461845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc2011-06-28T20:07:07ZEvan Chengevan.cheng@apple.com2011-06-28T20:07:07Zurn:sha1:22fee2dff4c43b551aefa44a96ca74fcade6bfac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc2011-06-27T18:32:37ZEvan Chengevan.cheng@apple.com2011-06-27T18:32:37Zurn:sha1:73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
Starting to refactor Target to separate out code that's needed to fully describe2011-06-24T01:44:41ZEvan Chengevan.cheng@apple.com2011-06-24T01:44:41Zurn:sha1:a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
move all the target's asmprinters into the main target. The piece 2010-11-14T18:43:56ZChris Lattnersabre@nondot.org2010-11-14T18:43:56Zurn:sha1:1139691e3aadff751c035f38f835d436ec6cf10a
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.2010-01-24T20:43:08ZChris Lattnersabre@nondot.org2010-01-24T20:43:08Zurn:sha1:43b5f9312d56be400af031f7487a99b75b7b0f97
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94378 91177308-0d34-0410-b5e6-96231b3b80d8