emscripten-fastcomp/lib/Target/XCore/Disassembler, branch masterLLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/XCore/Disassembler?h=master2013-05-05T13:20:22Z[XCore] Remove '-' from back branch asm syntax.2013-05-05T13:20:22ZRichard Osbornerichard@xmos.com2013-05-05T13:20:22Zurn:sha1:1114b0ec15aaa22dfc0ce582820cea556600d103
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Make use of the target independent global address offset folding.2013-05-04T17:24:33ZRichard Osbornerichard@xmos.com2013-05-04T17:24:33Zurn:sha1:6ffbf6ea8fe7fbe2166b07a88004baac163aa3c5
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] The RRegs register class is a superset of GRRegs.2013-04-04T19:57:46ZRichard Osbornerichard@xmos.com2013-04-04T19:57:46Zurn:sha1:c6ff29713d69b4a41c225cbde9c82e4a350dbfac
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add missing 2r instructions.2013-02-17T22:38:05ZRichard Osbornerichard@xmos.com2013-02-17T22:38:05Zurn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add TSETR instruction.2013-02-17T22:32:41ZRichard Osbornerichard@xmos.com2013-02-17T22:32:41Zurn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add missing l2rus instructions.2013-01-27T22:28:30ZRichard Osbornerichard@xmos.com2013-01-27T22:28:30Zurn:sha1:970a479c02a418726950580e13136acd2a2dc13f
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
Add instruction encodings / disassembly support for l4r instructions.2013-01-25T21:55:32ZRichard Osbornerichard@xmos.com2013-01-25T21:55:32Zurn:sha1:c47bd9899b639c3384268f871009259c2a94fba4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
Use the correct format in the STW / SETPSC instruction names.2013-01-25T21:25:12ZRichard Osbornerichard@xmos.com2013-01-25T21:25:12Zurn:sha1:1f375e5bc78647f9b29564eafdc907250ccd91ed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
Add instruction encodings / disassembly support for l5r instructions.2013-01-25T20:20:07ZRichard Osbornerichard@xmos.com2013-01-25T20:20:07Zurn:sha1:3b6a5eefe0ab2199bc69094b390b736ae332b905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
Add instruction encodings / disassembly support for l6r instructions.2013-01-23T20:08:11ZRichard Osbornerichard@xmos.com2013-01-23T20:08:11Zurn:sha1:9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8