LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/lib/Target/X86/MCTargetDesc?h=master 2013-07-24T16:40:15Z 2013-07-24T16:40:15Z Jim Stichnoth stichnot@chromium.org 2013-07-24T16:40:15Z urn:sha1:4499aac2b3679e7e0f69649b99f9b96c2c03dc4f Prevent sandbox addresses from being written to the stack. This covers the following cases: 1. Function calls manually push a masked return address and jump to the target, rather than using the call instruction. 2. When the function prolog chooses to use a frame pointer (rbp), it saves a masked version of the old rbp. 3. Indirect branches (jumps, calls, and returns) uniformly use r11 to construct the 64-bit target address. 4. Register r11 is marked as reserved (similar to r15) so that the register allocator won't inadvertently spill a code address to the stack. These transformations can be disabled for performance testing with the flag "-sfi-hide-sandbox-base=false". BUG= https://code.google.com/p/nativeclient/issues/detail?id=1235 R=eliben@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/19505003 2013-07-15T23:09:15Z Eli Bendersky eliben@chromium.org 2013-07-15T23:09:15Z urn:sha1:c6cf05cb5108f356dde97c01ee4188b0671d4542 Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp 2013-07-09T18:02:56Z Mark Seaborn mseaborn@chromium.org 2013-07-09T18:02:56Z urn:sha1:af49991972c1ca2364cd7377f4781893ffb3ffc5 Disable an assertion. This assertion made the behaviour on x86-32 inconsistent with x86-64 and ARM. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3548 TEST=*.ll tests + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/18261008 2013-05-10T23:00:11Z Derek Schuff dschuff@chromium.org 2013-05-10T23:00:11Z urn:sha1:52daf9d821c963f84dd312ff90921bfe1b1cc0a1 This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009 2013-04-25T19:27:05Z Rafael Espindola rafael.espindola@gmail.com 2013-04-25T19:27:05Z urn:sha1:93d0b06e2adca2d9f3d4ec544f352cc4e5e9618a Patch by Kai Nacke. This matches the gnu as output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-11T04:52:28Z Michael Liao michael.liao@intel.com 2013-04-11T04:52:28Z urn:sha1:02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-10T23:28:17Z Nico Rieck nico.rieck@gmail.com 2013-04-10T23:28:17Z urn:sha1:18d49acdab79d6f0966b47182b6c3a2ba3d9f80f Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-10T20:11:59Z Preston Gurd preston.gurd@intel.com 2013-04-10T20:11:59Z urn:sha1:15b64d0e28efc625bd740b19ad4138f48d5b98b0 into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179211 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-25T18:59:43Z Dave Zarzycki zarzycki@apple.com 2013-03-25T18:59:43Z urn:sha1:9b3939983fd0103b102c7aec0ed08d1e8bd28214 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-20T21:49:21Z Eli Bendersky eliben@chromium.org 2013-03-11T22:38:11Z urn:sha1:d41567d2ffd3413600162653c08b2365bd5bcbbf