emscripten-fastcomp/lib/Target/SystemZ/SystemZRegisterInfo.cpp, branch 1.14.1LLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/SystemZ/SystemZRegisterInfo.cpp?h=1.14.12013-05-06T16:15:19Z[SystemZ] Add back end2013-05-06T16:15:19ZUlrich Weigandulrich.weigand@de.ibm.com2013-05-06T16:15:19Zurn:sha1:1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target. Note that at this point, the target
cannot yet be built since the configure bits are missing. Those
will be provided shortly by a follow-on patch.
This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov. Thanks to all reviewers!
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the SystemZ backend.2011-10-24T23:48:32ZDan Gohmangohman@apple.com2011-10-24T23:48:32Zurn:sha1:29074ccf6cb00a3cbe32a3b7809d970ecaf8c9bf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down2011-07-18T20:57:22ZEvan Chengevan.cheng@apple.com2011-07-18T20:57:22Zurn:sha1:0e6a052331f674dd70e28af41f654a7874405eab
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
Next round of MC refactoring. This patch factor MC table instantiations, MC2011-07-14T20:59:42ZEvan Chengevan.cheng@apple.com2011-07-14T20:59:42Zurn:sha1:c60f9b752381baa6c4b80c0739034660f1748c84
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.2011-06-28T21:14:33ZEvan Chengevan.cheng@apple.com2011-06-28T21:14:33Zurn:sha1:d5b03f252c0db6b49a242abab63d7c5a260fceae
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
Hide more details in tablegen generated MCRegisterInfo ctor function.2011-06-28T20:44:22ZEvan Chengevan.cheng@apple.com2011-06-28T20:44:22Zurn:sha1:6844f7bcdec8c2691c8d1067d90e4a02cf658c27
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc2011-06-27T18:32:37ZEvan Chengevan.cheng@apple.com2011-06-27T18:32:37Zurn:sha1:73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
Starting to refactor Target to separate out code that's needed to fully describe2011-06-24T01:44:41ZEvan Chengevan.cheng@apple.com2011-06-24T01:44:41Zurn:sha1:a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
Remove custom allocation orders in SystemZ.2011-06-15T18:02:56ZJakob Stoklund Olesenstoklund@2pi.dk2011-06-15T18:02:56Zurn:sha1:b79e30cc9e8ce8c6beacbc38a7e27d33ba07fd66
Note that this actually changes code generation, and someone who
understands this target better should check the changes.
- R12Q is now allocatable. I think it was omitted from the allocation
order by mistake since it isn't reserved. It as apparently used as a
GOT pointer sometimes, and it should probably be reserved if that is
the case.
- The GR64 registers are allocated in a different order now. The
register allocator will automatically put the CSRs last. There were
other changes to the order that may have been significant.
The test fix is because r0 and r1 swapped places in the allocation order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133067 91177308-0d34-0410-b5e6-96231b3b80d8
Use the dwarf->llvm mapping to print register names in the cfi2011-05-30T20:20:15ZRafael Espindolarafael.espindola@gmail.com2011-05-30T20:20:15Zurn:sha1:6e032942cf58d1c41f88609a1cec74eb74940ecd
directives.
Fixes PR9826.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8