LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/lib/Target/PowerPC?h=master 2013-05-21T22:11:11Z 2013-05-21T22:11:11Z Bill Wendling isanbard@gmail.com 2013-05-21T22:11:11Z urn:sha1:3d3a37ed4d2bf264bd47a672efadd2f550f485f7 ------------------------------------------------------------------------ r182385 | hfinkel | 2013-05-21 07:21:09 -0700 (Tue, 21 May 2013) | 9 lines Fix PPC branch selection for counter-based branches Although I had added some support for the BDZ/BDNZ branches into the selector (in r158204), I had not correctly adjusted the condition at the top of the loop. As a result, these branches were still essentially unsupported. This fixes PR16086. Unfortunately, any test case would be very large (because it would need to force the loop backedge to exceed the range of the 16-bit immediate). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182431 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14T18:35:11Z Bill Wendling isanbard@gmail.com 2013-05-14T18:35:11Z urn:sha1:b1ecefd0b589689cf90b5346678989b997be1de7 ------------------------------------------------------------------------ r181450 | uweigand | 2013-05-08 10:50:07 -0700 (Wed, 08 May 2013) | 16 lines [PowerPC] Fix regression in generating @ha/@l relocs The patch I committed as revision 167864 introduced a regression that causes LLVM to no longer generate appropriate relocs for @ha/@l symbol references (but fail an assertion instead). This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/ VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in PPCELFObjectWriter.cpp. Tested by running projects/test-suite in -m32 mode with the integrated assembler forced on. A standalone test case will be committed shortly as well. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181816 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14T18:34:27Z Bill Wendling isanbard@gmail.com 2013-05-14T18:34:27Z urn:sha1:52b488a3f852bf0d4923441aab5fcf8cf518bebf ------------------------------------------------------------------------ r181800 | wschmidt | 2013-05-14 09:08:32 -0700 (Tue, 14 May 2013) | 15 lines PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181815 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-09T07:33:50Z Bill Wendling isanbard@gmail.com 2013-05-09T07:33:50Z urn:sha1:5f32469bd4d236a84313580c97085abb385ed605 ------------------------------------------------------------------------ r181423 | hfinkel | 2013-05-08 05:16:14 -0700 (Wed, 08 May 2013) | 5 lines PPCInstrInfo::optimizeCompareInstr should not optimize FP compares The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181507 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-06T11:16:57Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-06T11:16:57Z urn:sha1:7d55b6bb1a4a5220ef973cf7b68ae508859a9b71 As pointed out by Evgeniy Stepanov, assigning a std::string temporary to a StringRef is not a good idea. Rework MatchRegisterName to avoid using the .lower routine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181192 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:53:04Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:53:04Z urn:sha1:fcdfd5a7ffa2557753038fcbf421dd518e3fda98 PowerPC assemblers are supposed to support a stand-alone '$' symbol as an alternative of '.' to refer to the current PC. This does not work in the LLVM assembler parser yet. To avoid bootstrap failures when using the LLVM assembler as system assembler, this patch modifies the assembler source code generated by LLVM to avoid using '$' (and simply use '.' instead). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:51:09Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:51:09Z urn:sha1:8e4ba8f7b19615907e5874b3aa661d52c21fff74 This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:50:27Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:50:27Z urn:sha1:16adfdb2e666f46e058b603a8a7aa75758819fd5 This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-03T19:49:39Z Ulrich Weigand ulrich.weigand@de.ibm.com 2013-05-03T19:49:39Z urn:sha1:5e220753ff81ac5cbee874e7c00c76c7fbe0d20a This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-27T00:43:16Z Rafael Espindola rafael.espindola@gmail.com 2013-04-27T00:43:16Z urn:sha1:5b0ce3570c03919f71cab6ef8ed2312d2b707ca2 This fixes pr15763. Patch by David Fang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180657 91177308-0d34-0410-b5e6-96231b3b80d8