emscripten-fastcomp/lib/Target/PowerPC/InstPrinter, branch 1.14.0LLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/PowerPC/InstPrinter?h=1.14.02013-05-03T19:53:04Z[PowerPC] Avoid using '$' in generated assembler code2013-05-03T19:53:04ZUlrich Weigandulrich.weigand@de.ibm.com2013-05-03T19:53:04Zurn:sha1:fcdfd5a7ffa2557753038fcbf421dd518e3fda98
PowerPC assemblers are supposed to support a stand-alone '$' symbol
as an alternative of '.' to refer to the current PC. This does not
work in the LLVM assembler parser yet.
To avoid bootstrap failures when using the LLVM assembler as system
assembler, this patch modifies the assembler source code generated
by LLVM to avoid using '$' (and simply use '.' instead).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054 91177308-0d34-0410-b5e6-96231b3b80d8
PPC: Use HWEncoding and TRI->getEncodingValue2013-03-26T20:08:20ZHal Finkelhfinkel@anl.gov2013-03-26T20:08:20Zurn:sha1:aa6047d23d8ed55abd8545f5cbe82cd13cbd756a
As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
PowerPC: Use CCBITRC operand for ISEL patterns.2013-03-26T10:54:54ZUlrich Weigandulrich.weigand@de.ibm.com2013-03-26T10:54:54Zurn:sha1:a01c7dbaabae7cf569410bedd71361b75f65875f
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
PowerPC: Simplify BLR pattern.2013-03-26T10:53:27ZUlrich Weigandulrich.weigand@de.ibm.com2013-03-26T10:53:27Zurn:sha1:3b2552933642c19ce5e8836d82c26c562910e239
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002 91177308-0d34-0410-b5e6-96231b3b80d8
PR12716: PPC crashes on vector compare2012-10-08T18:59:53ZAdhemerval Zanellaazanella@linux.vnet.ibm.com2012-10-08T18:59:53Zurn:sha1:1c7d69bbe2de22f386ffd9ef4480f8a77be28130
Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.
This patch changes the behavior by just returning a DAG with the
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.
It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
Fix integer undefined behavior due to signed left shift overflow in LLVM.2012-08-24T23:29:28ZRichard Smithrichard-llvm@metafoo.co.uk2012-08-24T23:29:28Zurn:sha1:1144af3c9b4da48cd581156e05b24261c8de366a
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
Silence an unused variable warning on release builds.2012-06-23T08:09:30ZCraig Toppercraig.topper@gmail.com2012-06-23T08:09:30Zurn:sha1:0a2f793d6e24acd00d9209b46436b4899feb1cdb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for the PPC isel instruction.2012-06-22T23:10:08ZHal Finkelhfinkel@anl.gov2012-06-22T23:10:08Zurn:sha1:009f7afbeb77d1cc8e962bac7057b73b6d39d62f
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.2012-04-02T08:32:38ZBenjamin Kramerbenny.kra@googlemail.com2012-04-02T08:32:38Zurn:sha1:c97ef618d2d849a272a353c2b4343fc5902cd921
All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.2012-04-02T07:01:04ZCraig Toppercraig.topper@gmail.com2012-04-02T07:01:04Zurn:sha1:7c0b3c1fb6395475e262d66ee403645f0c67dee2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8