LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/lib/Target/Mips/MCTargetDesc?h=master 2013-07-15T23:09:15Z 2013-07-15T23:09:15Z Eli Bendersky eliben@chromium.org 2013-07-15T23:09:15Z urn:sha1:c6cf05cb5108f356dde97c01ee4188b0671d4542 Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp 2013-05-10T23:00:11Z Derek Schuff dschuff@chromium.org 2013-05-10T23:00:11Z urn:sha1:52daf9d821c963f84dd312ff90921bfe1b1cc0a1 This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009 2013-04-19T19:03:11Z Akira Hatanaka ahatanaka@mips.com 2013-04-19T19:03:11Z urn:sha1:f530aff9de2738db0e3471b259ff0b577a6603e6 This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-18T16:51:42Z Derek Schuff dschuff@chromium.org 2013-04-18T16:51:42Z urn:sha1:2f436965e5830fd3bc77d915c3598d47fe37a2a2 Clean up the LLVMBuild and CMakeLists.txt files BUG=none TEST=none Review URL: https://codereview.chromium.org/14328017 2013-04-17T00:18:04Z Jack Carter jack.carter@imgtec.com 2013-04-17T00:18:04Z urn:sha1:8afc8b7e63d5ce2d027e92934d16b19e5ba2db59 This patch allows the Mips assembler to parse and emit nested expressions as instruction operands. It also extends the expansion of memory instructions when an offset is given as an expression. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179657 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-11T01:23:13Z Petar Jovanovic petar.jovanovic@rt-rk.com 2013-04-11T01:23:13Z urn:sha1:29d2ddad89f1124216210a1e3fc9a216ed83f01c This change fixes some of the issues that came with recent merge with LLVM trunk, and it removes some workarounds that are not needed anymore in the code. In more details, it: - removes hack to set ELF::EF_MIPS_PIC flag; - checks whether __nacl_read_tp is defined in the module, as different relocation(s) is used to calculate the address; - marks Mips::JALRPseudo as indirect call in NaCl rewrite pass; - fixes incorrect merge in MipsAsmPrinter.cpp and MipsMCTargetDesc.cpp. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2275 TEST= run smoke tests Review URL: https://codereview.chromium.org/13601014 2013-03-22T00:29:10Z Jack Carter jack.carter@imgtec.com 2013-03-22T00:29:10Z urn:sha1:d3107fbc54a5b5156f0aabc8788724f1469eb9df For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-20T21:49:21Z Eli Bendersky eliben@chromium.org 2013-03-11T22:38:11Z urn:sha1:d41567d2ffd3413600162653c08b2365bd5bcbbf 2013-03-11T22:16:37Z Eli Bendersky eliben@chromium.org 2013-03-11T22:16:37Z urn:sha1:23c00401dad33ca247d2818e71540079bed63c5b Conflicts: include/llvm/CodeGen/LexicalScopes.h include/llvm/MC/MCAsmInfo.h lib/Linker/LinkArchives.cpp lib/Linker/LinkItems.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCDwarf.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/Mips/MipsTargetObjectFile.cpp lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86TargetMachine.cpp lib/Transforms/CMakeLists.txt lib/Transforms/LLVMBuild.txt lib/Transforms/Makefile test/MC/ARM/arm_instructions.s test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s 2013-02-20T07:39:18Z David Blaikie dblaikie@gmail.com 2013-02-20T07:39:18Z urn:sha1:5f645953555cee528cd1c0d6faa16d9b89ebba48 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175607 91177308-0d34-0410-b5e6-96231b3b80d8