emscripten-fastcomp/lib/Target/Mips/AsmParser, branch masterLLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/Mips/AsmParser?h=master2013-04-25T23:31:35ZMips assembler: .set reorder support2013-04-25T23:31:35ZJack Carterjack.carter@imgtec.com2013-04-25T23:31:35Zurn:sha1:97265a48895a2cda7f04e47bfe935c4fdd71f8ae
Mips have delayslots for certain instructions
like jumps and branches. These are instructions
that follow the branch or jump and are executed
before the jump or branch is completed.
Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.
The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.
For backwards compatibility we need to support
.set reorder and have it be the default behavior in the
assembler.
Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: formatting and comment changes.2013-04-18T00:41:53ZJack Carterjack.carter@imgtec.com2013-04-18T00:41:53Zurn:sha1:86924b4182537745659f2660244f3402c1e1ca4d
This patch should not have any functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179737 91177308-0d34-0410-b5e6-96231b3b80d8
Fix -Werror build.2013-04-17T06:45:11ZEvgeniy Stepanoveugeni.stepanov@gmail.com2013-04-17T06:45:11Zurn:sha1:ce47d5ba8cf7e30cbf0d6b80d3f7d10916c7fe31
Broken in r179657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179669 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: Enable handling of nested expressions2013-04-17T00:18:04ZJack Carterjack.carter@imgtec.com2013-04-17T00:18:04Zurn:sha1:8afc8b7e63d5ce2d027e92934d16b19e5ba2db59
This patch allows the Mips assembler to parse and emit nested
expressions as instruction operands. It also extends the
expansion of memory instructions when an offset is given as
an expression.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179657 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: Explicit floating point condition register recognition.2013-04-15T22:21:55ZJack Carterjack.carter@imgtec.com2013-04-15T22:21:55Zurn:sha1:b8145e3881872fffbac15693c94536446f060330
This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
This patch that enables the Mips assembler to use symbols for offset for instructions2013-03-22T00:05:30ZJack Carterjack.carter@imgtec.com2013-03-22T00:05:30Zurn:sha1:25df6a93f3324bd30f44dcb95fd17aff0a92d438
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
This patch enables the Mips .set directive to define aliases2013-03-21T21:44:16ZJack Carterjack.carter@imgtec.com2013-03-21T21:44:16Zurn:sha1:c91b5e197bb41ccb2f9f78b6176e61c848df9e15
The .set directive in the Mips the assembler can be
used to set the value of a symbol to an expression.
This changes the symbol's value and type to conform
to the expression's.
Syntax: .set symbol, expression
This patch implements the parsing of the above syntax
and enables the parser to use defined symbols when
parsing operands.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
Silence anonymous type in anonymous union warnings.2013-03-15T00:42:55ZEric Christopherechristo@gmail.com2013-03-15T00:42:55Zurn:sha1:a286fc065a5bc846d73c8407a534a1d3c1d70b59
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
Mips specific standalone assembler addressing mode %hi and %lo.2013-02-21T02:09:31ZJack Carterjcarter@mips.com2013-02-21T02:09:31Zurn:sha1:77217229ba1bbc92f3a53099fa91bcdaa7797da8
The constructs %hi() and %lo() represent the high and low 16
bits of the address.
Because the 16 bit offset field of an LW instruction is
interpreted as signed, if bit 15 of the low part is 1 then the
low part will act as a negative and 1 needs to be added to the
high part.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
ELF symbol table field st_other support, 2013-02-20T23:11:17ZJack Carterjcarter@mips.com2013-02-20T23:11:17Zurn:sha1:99e98551bf8719764f9345ce856118f3f1a9c441
excluding visibility bits.
Mips specific standalone assembler directive "set at".
This directive changes the general purpose register
that the assembler will use when given the symbolic
register name $at.
This does not include negative testing. That will come
in a future patch.
A side affect of this patch recognizes the different
GPR register names for temporaries between old abi
and new abi so a test case for that is included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175686 91177308-0d34-0410-b5e6-96231b3b80d8