emscripten-fastcomp/lib/Target/AArch64/Utils, branch masterLLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/lib/Target/AArch64/Utils?h=master2013-05-04T16:53:46ZAArch64: implement large code model access to global variables.2013-05-04T16:53:46ZTim NorthoverTim.Northover@arm.com2013-05-04T16:53:46Zurn:sha1:45db92038bf540fbbd8dfe5dff520aa8566d7cef
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.
For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
Fix undefined behavior in AArch642013-04-11T20:13:52ZDavid Majnemerdavid.majnemer@gmail.com2013-04-11T20:13:52Zurn:sha1:bae6d527dffbe302a8130ceb40b4e82cf61414b1
A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to
execute shifts that perform undefined behavior. Instead of attempting
to perform the 64-bit rotation, treat it as a no-op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179317 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: implement ETMv4 trace system registers.2013-04-03T12:31:29ZTim NorthoverTim.Northover@arm.com2013-04-03T12:31:29Zurn:sha1:4385f5dfced4e14bc59dfedb1f75116c0aabbc36
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: implement GICv3 system registers2013-03-28T14:30:46ZTim NorthoverTim.Northover@arm.com2013-03-28T14:30:46Zurn:sha1:42a1b2f0b196633c0327801e810fc98849a00c47
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
Add icache prefetch operations to AArch642013-02-06T09:04:56ZTim NorthoverTim.Northover@arm.com2013-02-06T09:04:56Zurn:sha1:9e3b31345f0d17b757e183a8384db92616256926
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
Fix formatting in AArch64 backend.2013-02-05T13:24:56ZTim NorthoverTim.Northover@arm.com2013-02-05T13:24:56Zurn:sha1:dfe076af9879eb68a7b8331f9c02eecf563d85be
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
Remove cyclic dependency in AArch64 libraries2013-02-05T13:24:47ZTim NorthoverTim.Northover@arm.com2013-02-05T13:24:47Zurn:sha1:19254c49a8752fe8c6fa648a6eb29f20a1f62c8b
This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174369 91177308-0d34-0410-b5e6-96231b3b80d8