emscripten-fastcomp/lib/CodeGen, branch 1.12.1

Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.

2013-10-11T22:27:57Z

See: http://llvm.org/viewvc/llvm-project?view=revision&revision=187787 The newer version of newlib tickles this x86-32 bug when building the exception handling tests, which don't strip the "tail" attribute. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702 Waiting on trybots, but it seems to have fixed the minimal reproducer I have: http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875 R=jfb@chromium.org Review URL: https://codereview.chromium.org/26538008

Apply upstream: Add missing ATOMIC_CMP_SWAP case.

2013-10-11T01:20:45Z

Cherry-pick r185186 from upstream. Original commit message: Author: Lang Hames Date: Fri Jun 28 18:36:42 2013 +0000 Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP. Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash during isel. This has to be cherry-picked, as we have experienced the same bug described in the original message. Missing case caused MIPS 64 atomics to crash. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= crash for MIPS atomics Review URL: https://codereview.chromium.org/26958002

Revert some ARM byval localmods since byval+varargs are not in stable pexes.

2013-08-30T23:42:36Z

Localmods came from: https://codereview.chromium.org/10825082/, and earlier. (1) The original change was so that byval parameters always go on the stack. That part was added because the original ARM code was buggy, and did not actually make a copy of the value, modifying the caller's struct (ouch!). (2) Then came a localmod to make all arguments following a byval go on the stack and to make the var-args code aware of that. This is so that arguments stay in the correct order for var-args to pick up. For (1) there has been some work upstream to make it work better. In any case, clang with --target=armv7a-...-gnueabi only used byval in some limited cases -- when the size of the struct is > 64 bytes where the backend will know that part of it could be in regs, and the rest can be memcpy'ed to the stack. For le32, clang will still generate byval without satisfying the same ARM condition (only for structs bigger than 64 bytes), so it could be *very bad* if we didn't have the ABI simpification passes rewrite the byval and try to let the ARM backend do things with byval... TEST=the GCC torture tests: va-arg-4.c, and 20030914-2.c and the example in issue 2746 still pass. BUG=none, cleanup R=dschuff@chromium.org Review URL: https://codereview.chromium.org/23691009

Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'

2013-07-15T23:09:15Z

Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp

Revert the IntrinsicLowering logic that preserves externals for intrinsics.

2013-06-28T20:25:56Z

This is no longer required, following our recent PNaCl ABI cleanups. BUG=None R=jvoung@chromium.org Review URL: https://codereview.chromium.org/18031017

Do not preserve abort() - it's not needed for ARM and X86.

2013-06-28T17:10:01Z

In a subsequent CL I'll clean up the whole IntrinsicLowering logic - probably reverting it to upstream since we no longer really use it. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3526 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/18053017

Do not preserve "pow" for the sake of re-materializing intrinsics.

2013-06-28T00:36:11Z

This is no longer required, since Clang will not generate llvm.pow.* intrinsics. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3513 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/18162002

Support for mem* library functions in stable bitcode via intrinsics.

2013-06-25T22:14:49Z

* Don't preserve external linking for mem{cpy,move,cmp} during LTO. * In the RewritePNaClLibraryCalls pass - add rewriting of mem* calls to appropriate intrinsics, similarly to the way it was done for longjmp. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3493 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/17622003

Fix PrologEpilogInserter to save and restore all callee saved registers

2013-06-13T23:04:07Z

if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002

Take some of the LLVM LibM intrinsics out of the "must be external" list.

2013-06-12T22:46:24Z

Intrinsic::sin, Intrinsic::cos, etc., aren't generated. Intrinsic::sqrt is implemented in hardware we support now. If future hardware does not support it, we can supply a library function in the runtime. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3339 TEST=scons, llvm test suite, gcc torture, spec2k R=eliben@chromium.org Review URL: https://codereview.chromium.org/16868002