emscripten-fastcomp/include/llvm/Target/TargetOpcodes.h, branch 1.14.1LLVM with the emscripten fastcomp javascript backendhttps://git.amat.us/emscripten-fastcomp/atom/include/llvm/Target/TargetOpcodes.h?h=1.14.12012-09-18T22:45:47ZFix Compile error on mac2012-09-18T22:45:47ZDerek Schuffdschuff@chromium.org2012-09-18T22:45:47Zurn:sha1:aa1912aafcdcf65105943faf7f60351855ac3756
Leftover from merge; mac gcc doesn't like trailing commas in enums.
TBR=jvoung@chromium.org
BUG=
Review URL: https://codereview.chromium.org/10943021
Merge commit '8e70b5506ec0d7a6c2740bc89cd1b8f12a78b24f'2012-09-18T22:07:33ZDerek Schuffdschuff@chromium.org2012-09-18T22:07:33Zurn:sha1:ef9bd62c68c2c279926e66058bc5a6ef62150432
Conflicts:
include/llvm/CodeGen/ISDOpcodes.h
include/llvm/Target/Target.td
include/llvm/Target/TargetLowering.h
include/llvm/Target/TargetOpcodes.h
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
lib/Target/Mips/MipsMCInstLower.cpp
utils/TableGen/CodeGenTarget.cpp
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be2012-09-06T09:17:37ZNadav Rotemnrotem@apple.com2012-09-06T09:17:37Zurn:sha1:c05d30601ced172b55be81bb529df6be91d6ae15
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
LOCALMODs from hg 0b098ca44de7 against r158408 (hg 90a87d6bfe45)2012-07-09T18:00:37ZDerek Schuffdschuff@chromium.org2012-07-09T17:52:46Zurn:sha1:5dbcc7e0c9c12f4a4042fb4a226654aee927999c
(only non-new files; new files in git 4f429c8b)
Change-Id: Ia39f818088485bd90e4d048db404f8d6ba5f836b
First chunk of MachineInstr bundle support.2011-12-06T22:12:01ZEvan Chengevan.cheng@apple.com2011-12-06T22:12:01Zurn:sha1:7c2a4a30e0e16762c75adacebd05ec9fcbccf16b
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.2011-06-16T18:17:13ZOwen Andersonresistor@mac.com2011-06-16T18:17:13Zurn:sha1:1300f3019e5d590231bbc3d907626708515d3212
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and2010-07-16T22:20:36ZBill Wendlingisanbard@gmail.com2010-07-16T22:20:36Zurn:sha1:7431beaba2a01c3fe299c861b2ec85cbf1dc81c4
thus is a much more meaningful name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
Remove TargetInstrInfo::copyRegToReg entirely.2010-07-11T17:01:17ZJakob Stoklund Olesenstoklund@2pi.dk2010-07-11T17:01:17Zurn:sha1:744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
Add a new target independent COPY instruction and code to lower it.2010-07-02T22:29:50ZJakob Stoklund Olesenstoklund@2pi.dk2010-07-02T22:29:50Zurn:sha1:a4e1ba53ddedd08669886b2849926bb33facc198
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up TargetOpcodes.h a bit, and limit the number of places where the full2010-07-02T21:44:22ZJakob Stoklund Olesenstoklund@2pi.dk2010-07-02T21:44:22Zurn:sha1:65766ce7df779ac0e7f6ee0171562b56769ae1dd
list of predefined instructions appear. Add some consistency checks.
Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8