emscripten-fastcomp/include/llvm/MC, branch master

Move global FlagSfi variables to common module

2013-10-30T12:16:42Z

When built as nexe, llc is configured and built for one arch only. Variables FlagSfiData, FlagSfiLoad, FlagSfiStore, FlagSfiStack, and FlagSfiBranch have to availabe for MIPS as well, so this change moves them from ARM-only code to common code. BUG= building pnacl-llc.nexe for MIPS fails TEST= build sandboxed tools for MIPS R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/46193002

Work around a gcc 4.6.3 / 4.7 bug.

2013-09-16T19:26:09Z

GCC bug http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416 causes the bf64-1.c test to fail in the GCC torture test suite. This provides an upstreamable workaround. Inspection of the LLVM code base showed no other instances of the pattern that triggers the gcc bug. This can also be upstreamed as soon as I can get a working x86-32 upstream build working to verify/test against. In the meantime, we can make one pnacl-fyi bot go green again. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3685 R=jfb@chromium.org, jfb@google.com Review URL: https://codereview.chromium.org/23437037

Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'

2013-07-15T23:09:15Z

Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp

Merging r181864:

2013-05-17T18:51:33Z

------------------------------------------------------------------------ r181864 | chapuni | 2013-05-14 19:16:23 -0700 (Tue, 14 May 2013) | 10 lines ELFRelocationEntry::operator<(): Try to stabilize the order. r_offset was insufficient to sort Relocs. It should fix llvm/test/CodeGen/ARM/ehabi-mc-compact-pr*.ll on some hosts. RELOCATION RECORDS FOR [.ARM.exidx]: 0 R_ARM_PREL31 .text 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 FIXME: I am not sure of the directions of extra comparators, in Type and Index. For now, they are different from the direction in r_offset. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182149 91177308-0d34-0410-b5e6-96231b3b80d8

LLVM: Add ELF Note section to NaCl object files identifying them as such to gold

2013-05-10T23:00:11Z

This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009

Add ArrayRef constructor from None, and do the cleanups that this constructor enables

2013-05-05T00:40:33Z

Patch by Robert Wilhelm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8

In MC asm parsing, account for the possibility of whitespace within

2013-05-03T00:15:41Z

the "identifier" parsed by the frontend callback by skipping forward until we've consumed a token that ends at the point dictated by the callback. In addition, inform the callback when it's parsing an unevaluated operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one (e.g. mov eax, [A::x]). This commit depends on a clang commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup and document MachineLocation.

2013-04-26T21:57:17Z

Clarify documentation and API to make the difference between register and register-indirect addressed locations more explicit. Put in a comment to point out that with the current implementation we cannot specify a register-indirect location with offset 0 (a breg 0 in DWARF). No functionality change intended. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180641 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused DwarfSectionOffsetDirective string

2013-04-22T22:49:11Z

The value isn't actually used, and setting it emits a COFF specific directive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180064 91177308-0d34-0410-b5e6-96231b3b80d8

[ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turn

2013-04-22T22:04:25Z

the MCParsedAsmOperand. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180054 91177308-0d34-0410-b5e6-96231b3b80d8