LLVM with the emscripten fastcomp javascript backend https://git.amat.us/emscripten-fastcomp/atom/include/llvm/IR?h=master 2013-08-07T22:50:54Z 2013-08-07T22:50:54Z JF Bastien jfb@chromium.org 2013-08-07T22:50:54Z urn:sha1:10c5d2cb2f5611441dae3114e3803526340e4b4b This is a follow-up to: https://codereview.chromium.org/22240002/ And requires the Clang changes from: https://codereview.chromium.org/22294002/ This new intrinsic represents ``asm("":::"~{memory}")`` as well as ``__sync_synchronize()``, and in IR it corresponds to a sequentially-consistent fence surrounded by ``call void asm sideeffect "", "~{memory}"()``. R=jvoung@chromium.org TEST= ninja check-all BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 Review URL: https://codereview.chromium.org/22474008 2013-08-06T23:14:36Z JF Bastien jfb@chromium.org 2013-08-06T23:14:36Z urn:sha1:77f169c9afeaf7384360ff6d56b73cc4d3200f5b This CL reworks memory ordering as specified by PNaCl. The documentation needed some clarification, and the implementation needs a bit more work around volatile and __sync_synchronize to offer stronger guarantees than what LLVM intends to offer for legacy code. There is a companion patch with Clang changes: https://codereview.chromium.org/22294002 R=eliben@chromium.org TEST= ninja check-all BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 Review URL: https://codereview.chromium.org/22240002 2013-08-01T22:06:01Z JF Bastien jfb@chromium.org 2013-08-01T22:06:01Z urn:sha1:a7665e96f34c4a981d59c78b0b872b8f0b100cb9 This is part of a bigger CL to fix C++11 in PNaCl, to commit in the following order: - https://codereview.chromium.org/20552002 - https://codereview.chromium.org/20554002 - https://codereview.chromium.org/20560002 - https://codereview.chromium.org/20561002 This should be the last PNaCl ABI change for C11/C+11 atomic support. Note that Clang already has a builtin for lock-free, but it's partly resolved by Clang's ExprConstant.cpp and CGBuiltin.cpp, whereas what we want is a call that becomes a constant at translation-time. I made the translation part fairly general so it's easy to support architectures where ``true`` isn't always the right answer. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 TEST= ./scons run_synchronization_cpp11_test --verbose bitcode=1 platform=x86-64 TEST= ninja check-all R=dschuff@chromium.org Review URL: https://codereview.chromium.org/20554002 2013-07-19T01:00:27Z Eli Bendersky eliben@chromium.org 2013-07-19T01:00:27Z urn:sha1:4412ea4b8e019d00dc7574fe1723eea0473a8ec1 2013-07-15T23:09:15Z Eli Bendersky eliben@chromium.org 2013-07-15T23:09:15Z urn:sha1:c6cf05cb5108f356dde97c01ee4188b0671d4542 Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp 2013-07-13T20:29:35Z JF Bastien jfb@chromium.org 2013-07-13T20:29:35Z urn:sha1:4c1316ea42eb48ec8da6753f3e0319b676e50a75 Add portable support for concurrency in PNaCl's ABI: - Promote volatile to atomic. - Promote all memory ordering to sequential consistency. - Rewrite all atomic operations to frozen NaCl intrinsics for pexe. - Rewrite atomic intrinsics to LLVM instructions for translation. This change also adds documentation to the PNaCl language reference, as well as tests where it makes sense. A future CL could clean up more of our code which mentions atomics, volatiles, memory orderings. Multiple reviewers because this is a big patch: - eliben: LLVM-fu and ResolvePNaClIntrinsics. - dschuff: ABI stability. - mseaborn: ABI stability. - sehr: Tron-duty (fight for the user's programs to work). BUG= https://code.google.com/p/nativeclient/issues/detail?id=3475 R=dschuff@chromium.org, eliben@chromium.org, sehr@google.com TEST= (cd ./pnacl/build/llvm_x86_64; ninja check-all) && ./pnacl/test.sh test-x86-32 && ./pnacl/test.sh test-x86-64 && ./pnacl/test.sh test-arm && ./pnacl/test.sh test-x86-32-sbtc && ./pnacl/test.sh test-x86-64-sbtc && ./pnacl/test.sh test-arm-sbtc Review URL: https://codereview.chromium.org/17777004 2013-06-13T23:04:07Z Derek Schuff dschuff@chromium.org 2013-06-13T23:04:07Z urn:sha1:c31b941a4fc4c995cbc40d5f4be6705d61eda011 if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002 2013-05-29T06:56:17Z Bill Wendling isanbard@gmail.com 2013-05-29T06:56:17Z urn:sha1:89d9794d4925de2d64cb0c821e11189cd8372b05 ------------------------------------------------------------------------ r182394 | jholewinski | 2013-05-21 09:51:30 -0700 (Tue, 21 May 2013) | 1 line [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182829 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14T22:06:43Z Eli Bendersky eliben@chromium.org 2013-05-14T22:06:43Z urn:sha1:8fe6f1f79c0d43752173a0aa8e752a3d21ea10f9 Intrinsic::getDeclaration and use the definition in include/llvm/Intrinsics.td This also makes the attribute on the intrinsic to be more consistent with the back-end (code-gen), which automatically assumes it's ReadNone (because this is what Intrinsics.td) defines. Using ReadNone rather than ReadOnly may be not strictly correct because the intrinsic depends on the value of the TP. However, this attribute is not really used anywhere in IR optimizations, and in the backend the intrinsic is ReadNone anyhow (the IR setting gets overridden). If we run into any problems with this in the future, we may consider handling the lowering of this intrinsic in TargetLowering::LowerINTRINSIC_W_CHAIN rather than in TargetLowering::LowerINTRINSIC_WO_CHAIN. BUG=None R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14643019 2013-05-09T22:16:09Z Eli Bendersky eliben@chromium.org 2013-05-09T22:16:09Z urn:sha1:42ac59f56fb0d473f84b6be738a64e80b09557d1 This is similar to the way @llvm.{set|long}jmp are handled. The previously defined nacl-specific intrinsics are no longer used and are overridden. For the library call, call setjmp/longjmp without a preceding underscore as these symbols exist in our runtime support code (pnacl/support/setjmp_XXX.S) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3429 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14715018