diff options
| -rw-r--r-- | lib/CodeGen/TargetInfo.cpp | 21 | ||||
| -rw-r--r-- | test/CodeGen/arm-arguments.c | 6 |
2 files changed, 18 insertions, 9 deletions
diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp index c8ec392bd1..4aa98d2fd8 100644 --- a/lib/CodeGen/TargetInfo.cpp +++ b/lib/CodeGen/TargetInfo.cpp @@ -2757,21 +2757,24 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty) const { } } + // FIXME: byval for AAPCS is not yet supported; we need it for performance + // and to support large alignment. + if (getABIKind() == ARMABIInfo::APCS) { + if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64) || + getContext().getTypeAlign(Ty) > 64) { + return ABIArgInfo::getIndirect(0, /*ByVal=*/true); + } + } + // Otherwise, pass by coercing to a structure of the appropriate size. - // - // FIXME: This doesn't handle alignment > 64 bits. llvm::Type* ElemTy; unsigned SizeRegs; - if (getContext().getTypeSizeInChars(Ty) <= CharUnits::fromQuantity(64)) { + // FIXME: Try to match the types of the arguments more accurately where + // we can. + if (getContext().getTypeAlign(Ty) <= 32) { ElemTy = llvm::Type::getInt32Ty(getVMContext()); SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; - } else if (getABIKind() == ARMABIInfo::APCS) { - // Initial ARM ByVal support is APCS-only. - return ABIArgInfo::getIndirect(0, /*ByVal=*/true); } else { - // FIXME: This is kind of nasty... but there isn't much choice - // because most of the ARM calling conventions don't yet support - // byval. ElemTy = llvm::Type::getInt64Ty(getVMContext()); SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; } diff --git a/test/CodeGen/arm-arguments.c b/test/CodeGen/arm-arguments.c index 1ca9a78e86..dd18414863 100644 --- a/test/CodeGen/arm-arguments.c +++ b/test/CodeGen/arm-arguments.c @@ -166,3 +166,9 @@ void f31(struct s31 s) { } // APCS-GNU: %s = alloca %struct.s31, align 4 // APCS-GNU: alloca [1 x i32] // APCS-GNU: store [1 x i32] %s.coerce, [1 x i32]* + +// PR13562 +struct s32 { double x; }; +void f32(struct s32 s) { } +// AAPCS: @f32([1 x i64] %s.coerce) +// APCS-GNU: @f32([2 x i32] %s.coerce) |