[4/6] ARM Neon Intrinsic Tablegen Test Generator.

Added code to NeonEmitter::runTests so that GenTest gets all of the needed
arguments to invoke the neon test generation methods.

Reviewed by Bob Wilson.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@179640 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 3 deletions

diff --git a/utils/TableGen/NeonEmitter.cpp b/utils/TableGen/NeonEmitter.cpp
index 257bf6572a..3b88020e5f 100644
--- a/utils/TableGen/NeonEmitter.cpp
+++ b/utils/TableGen/NeonEmitter.cpp
@@ -1700,7 +1700,8 @@ void NeonEmitter::runHeader(raw_ostream &OS) {
 static std::string GenTest(const std::string &name,
                            const std::string &proto,
                            StringRef outTypeStr, StringRef inTypeStr,
-                           bool isShift) {
+                           bool isShift, bool isHiddenLOp,
+                           ClassKind ck, const std::string &InstName) {
   assert(!proto.empty() && "");
   std::string s;
 
@@ -1772,10 +1773,13 @@ void NeonEmitter::runTests(raw_ostream &OS) {
     std::string Proto = R->getValueAsString("Prototype");
     std::string Types = R->getValueAsString("Types");
     bool isShift = R->getValueAsBit("isShift");
+    std::string InstName = R->getValueAsString("InstName");
+    bool isHiddenLOp = R->getValueAsBit("isHiddenLInst");
 
     SmallVector<StringRef, 16> TypeVec;
     ParseTypes(R, Types, TypeVec);
 
+    ClassKind ck = ClassMap[R->getSuperClasses()[1]];
     OpKind kind = OpMap[R->getValueAsDef("Operand")->getName()];
     if (kind == OpUnavailable)
       continue;
@@ -1790,10 +1794,12 @@ void NeonEmitter::runTests(raw_ostream &OS) {
           (void)ClassifyType(TypeVec[srcti], inQuad, dummy, dummy);
           if (srcti == ti || inQuad != outQuad)
             continue;
-          OS << GenTest(name, Proto, TypeVec[ti], TypeVec[srcti], isShift);
+          OS << GenTest(name, Proto, TypeVec[ti], TypeVec[srcti],
+                        isShift, isHiddenLOp, ck, InstName);
         }
       } else {
-        OS << GenTest(name, Proto, TypeVec[ti], TypeVec[ti], isShift);
+        OS << GenTest(name, Proto, TypeVec[ti], TypeVec[ti],
+                      isShift, isHiddenLOp, ck, InstName);
       }
     }
     OS << "\n";