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authorAkira Hatanaka <ahatanaka@mips.com>2012-05-11 21:56:58 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-05-11 21:56:58 +0000
commit91338cf4129cfdb85af7e9ef396ab09621da10ec (patch)
treeacd7e5f25e2840ef1415bc8a9ce0ba06295ed4e5 /test/CodeGen/mips64-class-return.cpp
parentdf8755884e039d3f313ee0fea42b955257b5e240 (diff)
Coerce byval aggregate arguments to integers whose size matches the integer
register size of the target architecture. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@156650 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/mips64-class-return.cpp')
-rw-r--r--test/CodeGen/mips64-class-return.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/mips64-class-return.cpp b/test/CodeGen/mips64-class-return.cpp
index dc9ec0f5be..8e32d5cbd6 100644
--- a/test/CodeGen/mips64-class-return.cpp
+++ b/test/CodeGen/mips64-class-return.cpp
@@ -39,7 +39,7 @@ void foo3(D2 a0) {
gd2 = a0;
}
-// CHECK: define void @_Z4foo42D0(%class.D0* nocapture byval %a0)
+// CHECK: define void @_Z4foo42D0(i64 %a0.coerce0, i64 %a0.coerce1)
void foo4(D0 a0) {
gd0 = a0;
}