IRgen: Fix case where we might generate an access component with width == 0, if

we have to narrow the access side immediately (can happen with packed,
-fno-bitfield-type-align).

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@102067 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 0 deletions

diff --git a/lib/CodeGen/CGRecordLayoutBuilder.cpp b/lib/CodeGen/CGRecordLayoutBuilder.cpp
index 17c5640c64..ee8ae5224f 100644
--- a/lib/CodeGen/CGRecordLayoutBuilder.cpp
+++ b/lib/CodeGen/CGRecordLayoutBuilder.cpp
@@ -215,6 +215,16 @@ static CGBitFieldInfo ComputeBitFieldInfo(CodeGenTypes &Types,
       std::min(AccessWidth - (AccessBitsInFieldStart - AccessStart),
                FieldSize - (AccessBitsInFieldStart-FieldOffset));
 
+    // If we haven't accessed any target bits yet and narrowed the access size,
+    // we might not have reached any target bits yet.
+    //
+    // FIXME: This test is unnecessarily once we choose the initial acccess size
+    // more intelligently.
+    if (!AccessedTargetBits && AccessBitsInFieldSize == 0) {
+      AccessStart += AccessWidth;
+      continue;
+    }
+
     assert(NumComponents < 3 && "Unexpected number of components!");
     CGBitFieldInfo::AccessInfo &AI = Components[NumComponents++];
     AI.FieldIndex = 0;